Impact of decoupling on power integrity

It is important for hardware designers to know the resonant frequency of each element (e.g., bulk bypass and decoupling capacitor, plane capacitance, and interconnect inductance) of the power distribution network (PDN), and its impact on power integrity (PI). A PCB with poor PI, e.g., having high PDN impedance at 50MHz and beyond, gives rise to simultaneous switching noise (SSN) and jitter of signals powered from the PDN. This article demonstrates the relationship between PDN impedance and SSN on a PCB.

Analysis and results
A prototype as diagrammed in figure 1 was implemented. The processor, with external 40MHz crystal oscillator, has three main interfaces: DDR2 SDRAM at 320Mbps data or 160MHz clock rate, parallel flash at 80MHz clock rate, and general purpose I/Os. All these components draw power from the buck converter. On the PCB, 0.1µF decoupling capacitors are placed right beneath the processor BGA on each power pin as shown in figure 2.

Figure 1: Block diagram of DUT.

Figure 2: Placement of decoupling capacitors under processor.

To show the relationship between PDN impedance and SSN, two test cases listed in the table were tried on the protype PCB. In test case A, a portion of the decoupling capacitors (shown in the red boxes in figure 2) is unloaded. On the other hand, all the decoupling capacitors are loaded for test case B.

Table: Decoupling conditions being studied.

First, the PDN impedance curves (simulated using Mentor Graphics Hyperlynx) from 10MHz to 500MHz are compared. Impedance for test case A is higher than case B due to the lower quantity of decoupling capacitators between Vcc and ground.