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Exploring Embedded DisplayPort

Posted: 18 May 2016     Print Version  Bookmark and Share

Keywords:the Video Electronics Standards Association  VESA  Embedded DisplayPort  eDP  LVDS 

Recent eDP developments focused on power reduction
Following eDP v1.3, which is commonly used for systems currently in production, eDP v1.4 was introduced in February 2013. eDP v1.4 included many new eDP-specific enhancements targeting further power reduction. One such feature is the partial frame update capability for PSR (PSR2). When the system is displaying a static image in self-refresh mode, such as text, and then just a portion of the image changes, such as the flashing cursor, partial frame update enables the GPU to only send that part of the image instead of the whole video frame (Figure 3). Another important and complementary upgrade is the ability to change the GPU power state more quickly. Enabling the GPU/CPU to quickly exit and enter the low-power state to make a selective image update saves system power.

Figure 3: Comparison between Panel Self Refresh (PSR) and PSR2 (updated version) operation. (Source: Parade Technologies)

eDP v1.4 was also the first video interface standard to leverage a form of display stream compression. This new category of image compression enables the reduction of bit rate and wire count on the video interface, saving power and reducing form factor. It can also be used to reduce the display's frame buffer size, reducing BOM cost. And eDP v1.4 expanded backlight control to regional backlight control to enable further power savings. Power was also reduced in the high-speed electrical interface that carries the video data. By adding more flexibility in voltage swing and data transport rate, the interface can be better optimized for the system design and display requirements.

Refining the standard
Since the publication of eDP v1.4 over two years ago, the PC OEMs working within VESA have continued to refine the standard and have been working toward production beginning in 2016. This led to the publication of the eDP v1.4a release in early 2015. Two influences for this updated release were the publication of the VESA Display Stream Compression (DSC) Standard v1.0 in March 2014, which was an improvement over the compression standard used in eDP v1.4, and the publication of DisplayPort Standard v1.3 in September 2014. Both of these new standards came after the release of eDP v1.4 in February 2013 and contributed important enhancements to eDP v1.4a. For example, the 8.1Gbps link rate defined in DisplayPort v1.3, coupled with DSC, enables 8K display resolution support.

eDP v1.4a also added Multi-SST Operation (MSO) to support a segmented panel display architecture (Figure 4). This enables a higher level of integration on high-resolution displays, allowing integration of the panel timing controller with source drivers, enabling thinner, lighter displays with a lower BOM cost. eDP v1.4a also added Y-coordinates to the PSR2 partial update command, relaxing time-base accuracy requirements in the display and thereby eliminating the crystal or crystal oscillator requirement originally required for an eDP v1.4 display – again, further lowering system BOM cost.

Figure 4: The eDP v1.4a specification supports Segmented Panel display architectures, which are designed to enable thinner, lighter and lower-cost panels that use less power. (Source: VESA, photo by Craig Wiley)


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