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Verification IP streamlines Micron HMC architecture design

Posted: 05 May 2016     Print Version  Bookmark and Share

Keywords:Synopsys  verification IP  Micron  HMC  DRAM 

Synopsys Inc. has released its next-generation verification IP (VIP) for Micron's Hybrid Memory Cube (HMC) architecture. According to the company, the VC VIP for HMC enables the design of modern high-speed memory technologies with ease of use, fast integration and optimum performance, expediting verification closure.

Synopsys VC VIP

The HMC architecture promises a high performance, low cost memory solution, with 70% less energy consumption than existing DRAM technologies.

Synopsys VC VIP for HMC uses a next-generation native SystemVerilog Universal Verification Methodology (UVM) architecture that enables ease of integration within existing verification environments to accelerate time to first test, detailed the Synopsys. The VC VIP for HMC is integrated with Synopsys' Verdi protocol analyser's memory-aware graphical debug solution and features advanced debug ports for easy and fast debug. Built-in coverage and verification plans are also included to speed up verification coverage closure.

VC VIP for HMC is available as a standalone product, and as part of the Synopsys VIP Library.

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