LPDDR4 DRAM memory controller compatible with DFI 4.0

Arastu Systems has introduced its LPDDR4 DRAM memory controller to address the rising demand for high performance and low power memories. The design IP supports popular industry standard AHB/AXI, but gives customers the flexibility to customise the design as per their needs, stated the company.

The controller is designed as per the JEDEC standard JESD209-4A and works seamlessly with partner's DFI PHY or DFI 4.0 compatible PHY from other vendors. The IP is developed using verilog and supports speeds up to 3200MTps (MegaTransfers per second) for applications where faster response rates and faster processors are mandatory, in order to achieve optimised end user experience.

The LPDDR4 IP solution also saves power by supporting multiple power saving modes such as self refresh power down, deep power down, thereby extending the battery life of consumer gadgets. It supports multiple channels and gives privilege to the user to configure and manage each channel independently and also maximises DRAM bus utilisation using Look-Ahead command processing and Bank Management.

Figure 1: LPDDR4 DRAM memory controller block diagram

The LPDDR4 DRAM controller facilitates secure access to memory thereby assuring protected data transfer mainly for applications such as advanced driver assistance systems (ADAS) and infotainment in the automotive industry, where security is the key concern. The core also supports DRAM testing, thereby increasing the system's reliability.