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Accelerate SoC verification with UVCs

Posted: 21 Mar 2016     Print Version  Bookmark and Share

Keywords:EDA tools  verification  Universal Verification Components  UVCs  ASIC 

Despite different methodologies developed in recent years and optimisation methods used in EDA tools to simulate large and complex designs, verification engineers frequently complain of performance issues because any latency in simulation is treated as the single biggest impediment to project deadlines. Dissatisfied with end results, design and verification (DV) engineers are collaborating to produce new ideas that can help reduce simulation time.

This paper by eInfochips discusses the effective usage of Universal Verification Components (UVCs) compared to certain third party IP blocks that results in huge time saving during the ASIC verification phase. Most SoCs are made of complex sub-blocks. Some are third party IPs like Memory Controllers, Standard Bus Protocols like AXI, Peripheral Components (Interconnect Express etc.) and some are proprietary blocks of chip design companies. Since third-party IPs used in complex SoCs are already silicon-proven, companies are least concerned about their in-depth verification.

However, as a standard industry practice, all proprietary blocks in semiconductor design have to be independently and properly verified. Most of the time, companies choose to verify these proprietary blocks at "Block level" itself considering the flexibility needed to verify all legal, erroneous and possible illegal scenarios. Some SoC level scenarios do not always make real sense but even then it is preferable to cover them in the block level verification program to detect any defects. DV Engineers may not experience that much simulation slowness for block level verification but when they move to Chip or SoC level verification, it starts becoming routinely common. Effective planning of certain things ahead while defining the Verification and Validation Environment helps clear certain major issues while leading to huge time saving without compromise.

What is UVC?
In the world of design verification, UVC is gaining immense popularity. UVC is a part of the Universal Verification Methodology (UVM) which has been endorsed by leading players such as Cadence, Mentor, and Synopsys. Informally, many engineers spell out the "UVC" abbreviation to denote "UVM Verification Component".

The role of the UVC on an interface is to either act as an interface driver (Active UVC) OR monitor (Passive UVC). It can also be both as it provides all controls necessary to simulate a design based on a desired functional scenario. In SoC Design Verification, it's common to have several UVCs sitting on different interfaces to drive/monitor signals based on respective interface protocols. Thus, an entire Verification Environment can be visualized with several UVCs as the primary building blocks.

Figure 1: Block diagram of an SoC design (partial)

Figure 1 shows part of an SoC design having multiple complex proprietary blocks (B0-B6) and third party customised IPs for AXI interconnect and DDR4 Controller blocks. Blocks B0-B4 act as AXI Write or Read Master depending upon the kind of requests they made to DDR4 controller. AXI bus interface is used for on-Chip communication. D128/256 represents the width (either 128 or 256 bits) of the Data Line and A32 represents the width of Address Line. B0 and B4 have instance of AXI Write Masters, B2 has AXI Read Master and B1 and B3 have both AXI Write and Read Master Instances. AXI interconnect sends all the requests from B0 to B4 masters to corresponding requests on Slave P0 to P4 ports of the DDR4 Controller block which is connected to DDR4 memory. AXI interconnect implements a flow control mechanism to generate the back pressure depending on the bandwidth it has to serve multiple requests from B0-B4.

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