Rocket scientist's guide to decoupling (Part 1)

You are developing your latest sub-system and somebody instructs you to place as many 100 nF decoupling capacitors as you can, as close as physically possible to all the integrated circuits, just like we did on our last satellite. As a design engineer, it's only natural to question this qualitative approach to decoupling. What is its purpose? Why 100 nF? What about other values? How many capacitors? How close to the chip and in what orientation?

Did you know that in some instances you can remove many of the decoupling capacitors on your PCB without impacting the performance or the reliability of your sub-system? How do you optimise de-coupling, avoid over-engineering your design, reduce the BOM, and deliver less expensive and more reliable hardware, right-first-time?

Why decouple?
The purpose of a power distribution network (PDN) is to deliver defined, regulated voltages to each of the integrated circuits it has to supply. However, between a DC-DC converter and its load, there are lots of interconnects within the PDN; e.g. traces, pads, vias, planes, package leads, bond wires, etc, as illustrated in figure 1.

If the current draw by each chip was constant, this would result in a constant IR drop within the PDN due to the series resistances of the various interconnects. However, the transient demands of integrated circuits vary at each clock cycle and the impedance of a PDN includes inductive and capacitive elements. A rapidly-changing current passing through a complex impedance will generate a voltage drop known as rail droop or rail collapse, with the potential to cause excess ripple, regulator instability, reduced timing margin, brownout, or functional failure if the capacitor is unable to supply its load with the required current. The droops inject noise into the power and ground planes emitting unwanted EMI at the edges of a PCB, and decoupling also reduces this interference.

A regulator has a much slower response to transient current demands than the operational speed of the device it powers. The purpose of bypass or decoupling capacitors within a PDN is to eliminate transient voltage drops by storing electric charge, which is released during a droop. The role of decoupling is to provide this capacitance to each integrated circuit with the minimum of parasitic impedance over a wide range of frequencies. The overall loop inductance determines how fast the charge can be delivered from the PDN to the load and each capacitor introduces intrinsic ESR and ESL, as well as unwanted mounting, via, and plane-spreading inductances. The goal of PDN design is to maximise the effectiveness of the capacitance by minimising inductance, thus keeping the impedance below a target value over the required bandwidth. This restricts any variation of the supply rails to an acceptable, specified limit, e.g. 5% ripple.

The space industry wants to avail itself of the performance advantages of ultra deep subµm integrated circuits that require low voltage, high current supply rails. These chips operate at faster frequencies and as they switch more often, the energy consumed during each cycle is also expended more frequently. Combining all of these means that higher currents will be changing in shorter amounts of time and the relative amount of noise which can be tolerated will decrease.

How much decoupling?
When designing the PDN, the goal should be to select the minimum number of decoupling capacitors that will ensure the impedance remains just below the target value over the required bandwidth.