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III-V nanowires on CMOS target next-gen 5G, radar systems

Posted: 08 Mar 2016     Print Version  Bookmark and Share

Keywords:IBM  5G  radar  CMOS  III-V nanowire 

A $4.7 million programme in EU aims to incorporate III-V transistor channels on standard CMOS aimed to meet the needs of future 5G and radar systems for wider bandwidth and higher-resolution images, respectively. Called "Integration of III-V Nanowire Semiconductors for Next Generation High Performance CMOS SoC Technologies" (Insight), the programme will be conducted by IBM (Switzerland), Fraunhofer IAF (Germany), LETI (France), Lund University (Sweden), University of Glasgow (UK) and the Tyndall National Institute (Ireland).

There will be two phases to the program led by IBM and Lund University, with IBM concentrating on prototyping conventional planar transistors with III-V channels, whereas Lund University will investigate the feasibility of vertical III-V transistor channels.

"First the partners will decide together whether the horizontal or vertical transistor prototypes are the most promising," IBM scientist Lukas Czornomaz said. "Then we will work together to deliver an RF [radio frequency] test circuit, such as a PA [power amplifier] by the end of the three-year programme."

III-V integrated on silicon

Figure 1: Scanning electron microscope images of single crystal structures fabricated using IBM's template-assisted selective epitaxy—silicon is coloured in green and the III-V semiconductor in red. (Source: IBM, used with its permission)

IBM is confident that its planar method will work, because it has already demonstrated its feasibility at below 14nm in a paper last year titled IBM Scientists Present III-V Epitaxy and Integration to Go Below 14nm.

The way IBM's process works is by what they call "template-assisted selective epitaxy." They grow an oxide wire where they want the III-V transistor channel to eventually be for a gate-first CMOS-compatible III-V FinFETs on silicon substrates. Next they coat the nanowire with the III-V material so that it only touches the substrate in just a nanoscale or even angstrom-scale area. Lastly, they removed the oxide from inside the III-V coated nanowire, thus resulting in a III-V nanotube transistor channel in precisely the correct position.

III-V integrated on silicon

Figure 2: Cross-sectional transmission electron microscope (TEM) imager of III-V integrated on silicon using IBM's technique (a). The high number of defects in the seed region (b,c) consist of stacking faults, but away from the seed, a perfect lattice structure is observed with an eight per cent mismatch to silicon resulting a fully relaxed III-V (d,e). (Source: IBM, used with permission)

IBM predicts mm-wave RF performance at a much lower power consumption level than today, facilitating not just 5G but also cognitive computers, next-generation Internet of Thing (IoT) and the cloud-based platforms supporting them.

Insight's stated goals are to scale CMOS beyond the 7nm node thereby opening up a whole new range of applications serviced by ultra-high-performance SoCs. The other partners, Fraunhofer, Fraunhofe, LETI, Lund University, University of Glasgow and the Tyndall National Institute also all have III-V on CMOS expertise that they will bring to bear on the project.

Insight is funded under the E.U.'s Horizon 2020 Programme for Research and Development (grant number 688784).

- R. Colin Johnson
  EE Times

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