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Grasping high bandwidth memory PHY verification

Posted: 09 Mar 2016     Print Version  Bookmark and Share

Keywords:High bandwidth memory  HBM  PHY  DRAM  memory controllers 

Full randomisation, timing control, seamless transactions, row-col commands control & few mode operations are not supported though, by the memory controller. Hence, there may be coverage loopholes in functional verification. To achieve full randomisation, timing control, Command Control System Verilog –UVM based DFI UVC is used to drive DFI signals.

HBM memory to receive DRAM write-reads
Vendor-specific HBM memory can be used to connect with HBM PHY with HBM JEDEC interfaces. This HBM memory will receive HBM commands, data, data mask, parity etc. from HBM PHY. Generally, all memory models are providing in-built protocol assertions. Each HBM device will have vendor-specific features, functions and timings. HBM memory model will be encrypted in VCS/IUS/Questa tool; hence, verification environment should be compatible with all the tools. HBM PHY should be verified with respect to all supported features of HBM memory.

DFI Monitor, HBM Monitor
DFI monitor will capture row-col address; write data, read data, data mask, data bus inversion etc. information from DFI interface. During write operation, it will store the write data based on DBI and DM value, and during read operation it will compare the read data with the previously stored write data. Similarly HBM monitor will only capture the row-col addresses, write data, read data, data mask, data bus inversion etc. information residing in HBM DRAM interface. No need to do Memory write-read comparison in HBM monitor as DFI monitor is doing the same. DFI monitor should support both frequency ratios one and two. Both monitors are developed in UVM methodology and provide the HBM packet for other verification component.

Scoreboard between DFI interface and DRAM interface
Scoreboard will get a HBM packet from DFI monitor and HBM monitor. HBM packet from DFI monitor is compared with HBM packet from HBM monitor in case of write transfers. HBM packets from HBM monitor is compared with HBM packet from DFI monitor.

Verification challenges
 • Mostly, behavioural memory models are encrypted so debugging remains a challenge. But any HBM DRAM timing violations will be logged by memory assertions. DFI, HBM monitor and Scoreboard will help debug the issues.
 • Frequency ratio 1:2 Implementation in DFI driver and DFI monitor. DFI interfaces need to drive the signals on 2 different phases (P0 & P1) with half the frequency of HBM clock frequency.
 • Feature limitations of Memory controller and other memory devices will not allow fully functional verification of HBM PHY. Limitations in memory controller can be overcome by DFI UVC which means different memory models can be integrated in the test bench to cover full functionality.
 • Verification environment should be tool (VCS, IUS, Questa)-independent as memory models may be encrypted in any tool – IUS, VCS, Questa. System Verilog–UVM-based verification environment will provide a tool-independent platform.
 • Handling seamless writes/reads for Full-speed and Half-speed mode, in DFI driver, DFI Monitor, HBM monitor requires systematic architecture.
 • Test-chip level verification is required to initialise and configure all the memory controllers with APB interfaces which takes around 10 minutes of simulation time. Hence, debugging time will increase.

Common issues
 • Timing violations and write-read latency limitations of memory model will generate wrong read data, mostly "x".
 • Gate level simulations will produce "x" for the uninitialized flops inside the design. Tool & Design specific initialisation with switches to initialise all flops with some known value will help to overcome this

An HBM PHY can be verified at block level and test-chip level using this verification strategy. Some of the challenges and common issues mentioned will help in verification architecture planning and development. Most companies however are facing struggles with the verification of the HBM PHY layer due to lack of an efficient verification strategy, and timeline pressures from multiple end customers.

About the authors
Ankit Sheth and Jignesh Oza are with eInfochips.

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