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Grasping high bandwidth memory PHY verification

Posted: 09 Mar 2016     Print Version  Bookmark and Share

Keywords:High bandwidth memory  HBM  PHY  DRAM  memory controllers 

Memory systems have undergone major transformation in the previous few years due to advancements in fabrication technology. High bandwidth memory (HBM) is an example of the latest kind of memory chips which can support low power consumption, ultra-wide communication lanes, and stacked configurations. HBM sub-systems involve different types of memory controllers (full-speed, half-speed), HBM PHY, and HBM DRAM. The HBM sub-system is suitable for applications involving high performance graphics and computing, high end networking and communication devices, and memory-hungry processors. Because of their critical end-application role, it is crucial to verify all design components involved in HBM sub-systems. Here, we will discuss the role of the HBM PHY, along with the major verification aspects/challenges.

The HBM PHY is a key element in an overall HBM system solution. HBM PHY generally receives HBM DRAM row-col commands, data, parity, etc. from memory controllers through DFI interfaces and passes them to HBM memory along with the use of HBM DRAM interface. It deals with two different interfaces and supports multiple frequency ratios for DFI interfaces. HBM PHY is ideally required to support all HBM memory features like frequency ratios, data rates, memory sizes, pseudo channel modes, legacy modes, DBI, DM etc. HBM PHY can be verified at the sub-system level and block level with different, vendor-specific memory controllers and HBM memories.

Figure: Verification strategy flow.

Verification strategy
To verify HBM PHY design, we need the following components: HBM Memory controller or DFI driver UVC (Universal Verification Component) to drive a DFI interface:

DFI interface signals may be implementation-specific but they should follow what is known as a DFI3.1 protocol. Vendor-specific memory controllers can be single port or dual port. DFI interfaces involve phase 0 and phase 1 signals for Control Interfaces, Write Data Interfaces, Read Data Interfaces, Update Interfaces, Status Interfaces and Training Interfaces. When frequency ratio one is selected, the controller will drive on only phase 0 signals (*p0) at the same frequency as HBM DRAM memory clock frequency. Controllers supporting frequency ratio two will drive on both phases: phase0 (*p0) and phase1 (*p1) at half the frequency of DRAM memory clock frequency.

AMBA APB bus can be used to configure and initialise the memory controller for HBM DRAM features like DM, DBI, latencies etc. Memory addresses and data can be provided using AMBA AXI bus or any vendor-specific interface. Once the memory controller is initialized and configured through the APB interface, the memory controller will get read-write address and write data through AXI bus or other vendor-specific interfaces. APB/AXI/vendor-specific UVC will be used as a configuration and data driver for the memory controller.

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