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Mirabilis Design library enables memory controller dev't

Posted: 02 Feb 2016     Print Version  Bookmark and Share

Keywords:Mirabilis Design  memory controller  DRAM  modeling library 

Mirabilis Design Inc. has rolled out the VisualSim Memory modeling library that contains all current and prior versions of DDR, LPDDR, HBM, SRAM, JEDEC-complaint memory controller and a generic memory controller. According to the company, system designers and architects use this library to develop novel memory sub-systems, explore additional standards and algorithms, and optimise the memory access for their target application.

The solution has been used to conduct trade-off between different speed/variations of DRAM, performance versus power, and memory bandwidth efficiency. "Memory interface design and analysis is the biggest demand from our system-level customer base," said Deepak Shankar, founder of Mirabilis Design. "This library is a first of its kind and contains all the required models in one folder. Our customers are using these blocks to architect deterministic read/write latency and maximise battery life."

VisualSim Memory can be used with VisualSim resource, behaviour and cycle-accurate modeling libraries to construct models, simulate and analyse the complete system or SoC. This library is used to validate proposal, conduct trade-off decisions, timing, throughput, arbitration algorithm, power consumption analysis, and study systems behaviour with different configuration (single versus dual channels, clock speed variations, addressing schemes and controller algorithms).

Features of the library include: DRAM blocks available are DDR2, DDR3, DDR4, LPDDR2, LPDDR3, LPDDR4 and SRAM; storage blocks available are Flash and SSD; latest technology available are NVM and HBM; and memory controllers available are JEDEC-standard, multi port-multi channel and generic.

VisualSim Memory Modeling Library

VisualSim Memory Modeling Library

Mirabilis Design Memory Library enables both SoC and systems architects to design memory controllers, maximise memory efficiency for performance-critical applications and lower power consumption. The library offers statistical and cycle-accurate cache; packs memory controller and RAM blocks that can be combined with the processor, RTOS, buses, interfaces, traffic generators and other architecture components to assemble the entire system; and the modeled systems can be simulated for a variety of interface speeds, traffic rates, memory capacity, controller attributes, vendor-specific timing.

VisualSim Memory Modeling Library is available for $5,000 in U.S. This library requires VisualSim Architect to construct models and simulate. The product is supported on Windows, Linux and Mac OS/X.

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