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Enhance timing correlation to synthesis

Posted: 02 Feb 2016     Print Version  Bookmark and Share

Keywords:physical design  timing  floorplan  resistance  capacitance 

The design of a chip entails many stages, from system specification and architectural design, all the way to the fabrication and packaging of the final silicon that goes into a device. During this cycle, it is crucial to have reliable estimates of timing and area in order to plan properly and meet expectations. This article will take a look into the physical design (or backend design) portion of the process; specifically, at the correlation of timing and area within the steps associated with the physical design.

Correlation problems between synthesis and placement
Large designs may take many days to run through the full physical design flow. Thus, it is valuable to have the ability to give early feedback to the design and architecture teams, to develop timing constraints, and to have the freedom to explore floorplan options quickly. In order to achieve these goals, it's imperative to have reliable estimates of timing and area.

Figure 1: Integrated Circuit (IC) design flow and physical design steps (Source: CEVA).

In the past, we've had reasonably good correlation between synthesis placement and route. For timing, the accuracy would be around 3% to 4%, with even better results for area. In new and advanced processes, however, starting at the 28 nm process node, we've been experiencing more and more cases of unexpected results. Not only have we seen larger gaps between the physical synthesis results to the actual timing in placement-and-route, but some timing paths became significantly faster, while others became much slower. This was quite puzzling. When looking at the area, the results were even more alarming. From synthesis to layout, the correlation had become quite poor, as illustrated in the following image:

Figure 2: Synthesised cell density in the floorplan stage (top) as compared to the placement stage (bottom) (Source: CEVA)

The above images are cell density maps taken from the CEVA-XM4 core, comparing the cell density in synthesis (top) to the cell density at placement (bottom). The orange sections in the placement image show a critical increase in area. The overall increase in area, in this case, was around 18%. This is quite bad, but perhaps not intolerable. However, after taking into account that most of the design is fixed area (memory and registers), which does not change at all from synthesis to layout, it becomes clear that certain parts are really going through the roof. When we isolated the buffer cells areas, we observed an increase of 118% over the synthesised area, meaning that the buffer count and area had more than doubled.

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