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Speed up FPGA development times

Posted: 29 Jan 2016     Print Version  Bookmark and Share

Keywords:FPGA  Synplify  RTL  embedded software  parallelism 

However, there is a growing need to further accelerate runtimes beyond what the compile point technology provides. Newer, larger devices are lengthening runtimes significantly, and designers are finding that they need synthesis tools that enable much faster runtimes to achieve their design schedules. This translates to the number of iterations-per-day designers can achieve to support incremental changes to the full FPGA design, which are a necessity to support hardware validation and accelerate the development of embedded software. The latest version of Synplify provides customers with advanced distributed synthesis technologies that provide a 3x boost in runtimes and productivity. Distributed synthesis takes the compile point concept to the next level—employing distributed processing across multiple cores and multiple machines—throughout the entire synthesis flow for easy deployment to server farms.

Figure 2: Enabling server farm distributed synthesis with multi-processing (Source: Synopsys).

As the overall FPGA design increases in size and complexity, Synplify provides a scalable flow that is able to handle increasing design complexity and sizes. In conjunction with faster runtimes with distributed synthesis, the overall memory footprint is decreased.

The Synplify compile point flow allows parallelism in processing; however the achieved benefit is limited. The distributed synthesis technology allows designers to design much larger and complex FPGA designs while continuing to accelerate runtimes. This provides a significant productivity gain and helps to achieve the ever shrinking design schedules. As FPGA designs become bigger and more complex, distributed synthesis becomes the obvious choice for creating FPGA designs quickly.

About the author
Joe Mallet is with Synopsis.


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