Speed up FPGA development times
Keywords:FPGA Synplify RTL embedded software parallelism
• Longer run times due to increasing design size and complexity.
• Achieving rapid synthesis turn-around time to integrate design changes.
• Avoiding unnecessary resynthesising of pre-verified, static modules, like IP blocks and completed modules.
In order to achieve accelerated FPGA development schedules, while supporting increasing design sizes and complexity, designers require the aid of sophisticated synthesis tools.
Many years ago, Synplify FPGA synthesis software introduced a capability that allowed designers to automatically or manually create RTL partitions ("compile points") in their FPGA designs. Designers utilising compile points could develop modules separately, add incremental features to be incorporated, and complete incremental synthesis of designs. This boosted productivity and design closure because it allowed designers to synthesise a module once, and only resynthesise those parts of the design that changed.
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Figure 1: Fast initial and incremental runtimes using compile point technology (Source: Synopsys). |
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