Global Sources
EE Times-India
Stay in touch with EE Times India
EE Times-India > FPGAs/PLDs

Speed up FPGA development times

Posted: 29 Jan 2016     Print Version  Bookmark and Share

Keywords:FPGA  Synplify  RTL  embedded software  parallelism 

FPGA device density continues to rise at approximately twice per node, which is—not surprisingly—leading to larger, more complex designs. This means that FPGA designers face several challenges as follows:
 • Longer run times due to increasing design size and complexity.
 • Achieving rapid synthesis turn-around time to integrate design changes.
 • Avoiding unnecessary resynthesising of pre-verified, static modules, like IP blocks and completed modules.

In order to achieve accelerated FPGA development schedules, while supporting increasing design sizes and complexity, designers require the aid of sophisticated synthesis tools.

Many years ago, Synplify FPGA synthesis software introduced a capability that allowed designers to automatically or manually create RTL partitions ("compile points") in their FPGA designs. Designers utilising compile points could develop modules separately, add incremental features to be incorporated, and complete incremental synthesis of designs. This boosted productivity and design closure because it allowed designers to synthesise a module once, and only resynthesise those parts of the design that changed.

Figure 1: Fast initial and incremental runtimes using compile point technology (Source: Synopsys).

1 • 2 Next Page Last Page

Comment on "Speed up FPGA development times"
*  You can enter [0] more charecters.
*Verify code:


Visit Asia Webinars to learn about the latest in technology and get practical design tips.


Go to top             Connect on Facebook      Follow us on Twitter      Follow us on Orkut

Back to Top