DFT boot camp, Part 4: Built-in self-test(3)

In addition to having BIST solutions operate under functional power constraints, be aware that these solutions operate correctly in the presence of low-power design features. A good example of where this requirement is important is in relation to on-chip memory repair. The basic self-repair architecture breaks down when voltage islands or power domains are used. This popular power management approach involves using a separate supply voltage for each core (or, possibly, group of cores) within a design. Each resulting power domain can then be shut down when not in use and re-activated when needed. This powering up and down activity has a direct effect on repairable memories. When a sleeping power domain is re-activated, the repair information for the repairable memories in that domain will have been lost and will need to be reloaded. The challenge here is that the reloading has to occur without disrupting the already active domains, and the reloading can't be affected by the fact that some domains may still be inactive.

To handle these constraints, the self-repair architecture described above has to be augmented to provide at least one repair shift chain for each power domain, as illustrated in figure 5. Each shift register can be of arbitrary length. A functional power management unit indicates to the fuse controller which shift register(s) need(s) to be loaded. The other shift registers are kept in a stable state as they might contain repair information for active power domains.

Figure 5: Power-aware built-in self-repair uses shift registers.

When multiple domains are reactivated, the controller will generally need to load them sequentially according to a default priority defined at design time. The operation is sequential because all repair information is typically stored in the same fuse array. If the loading order needs to be changed, the power management unit simply needs to reactivate each island one at a time in the desired order. The functional power management unit and the fuse controller must both be in an always-on power domain while the various MBIST controllers and repair registers are placed within the same power domains as the memories they service. Power domains can span multiple physical regions and a physical region can also contain multiple power domains.

Hybrid ATPG-LBIST
Because automotive and medical designs need high reliability in the field, they must be being tested with a combination of both pseudorandom LBIST patterns and deterministic ATPG (automatic test-program generation). With this hybrid ATPG/LBIST test technique, you can use ATPG to achieve very low DPM (defects per million), checking for small delay, cell-aware, and path delay types of defects. LBIST can also be used in post-manufacturing environments such as burn-in, system-level test, and in-field self-test. The ability of a device to periodically test itself in the field is a necessity in many safety critical applications, and is required to satisfy the reliability requirements specified within the ISO 26262 automotive safety standard.

Hybrid ATPG/LBIST solutions can share on-chip DFT resources such as scan chains and clock control logic. Also, the on-chip controller logic for both ATPG compression and LBIST can be integrated into a single block that is significantly smaller than the two separate implementations. The combined architecture provides the ability to apply combinations of compressed ATPG and random LBIST patterns. A single DFT automation flow enables both a flat as well as hierarchical integration of the hybrid capabilities. Such a flow can incorporate design rule checking, hybrid controller insertion and verification, scan insertion, and fault simulation integrated across both pattern types. A hybrid ATPG/LBIST controller can be accessed through a standard IEEE 1687 network, allowing easier access to the embedded test capabilities from anywhere in the system.

About the author
Ron Press is the technical marketing manager of the Silicon Test Solutions products at Mentor Graphics. The 25-year veteran of the test and DFT (design-for-test) industry has presented seminars on DFT and test throughout the world. He has published dozens of papers in the field of test, is a member of the International Test Conference (ITC) Steering Committee, and is a Golden Core member of the IEEE Computer Society, and a Senior Member of IEEE. Press has patents on reduced-pin-count testing and glitch-free clock switching.