DFT boot camp, Part 4: Built-in self-test(2)

During LBIST execution, all the scan-chain flops in a circuit must capture a known (expected) state for each pattern. Any unknown values (referred to as Xs) that can occur in the circuit and captured into the scan chains will corrupt the MISR and LBIST results. If Xs are discovered during design, they can be eliminated by suitable initialisation or masking techniques in the circuit. for Xs that are only discovered after fabrication, however, you need to mask corrupted scan chain results so they don't affect the MISR signature.

Consequently, LBIST tools include chain masking features so you can effectively test the rest of the circuit using logic BIST in the presence of a bad chain.

Memory BIST
Most designs todays include a large number of embedded memories. You typically need additional circuitry to allow an external tester to access each embedded memory through the external I/O pins of the IC. This can negatively impact chip routability, area, performance, and design cycle time.

MBIST (memory BIST) eliminates the design effort needed to make embedded memories accessible for external test and provides at-speed self-test using algorithmically generated memory testing patterns. A serial data interface enables communication between multiple embedded random access memories (RAMs) and an MBIST controller. For testing very large memories or to achieve very short test times, MBIST can employ a parallel data interface (figure 3).

Figure 3: A typical Memory BIST architecture.

An MBIST DFT (design-for-test) tool generates a test structure (MBIST control logic) for one or more embedded memories. It also includes a simulation test bench in Verilog for design verification and shell scripts to drive synthesis of the RTL (resistor-transistor logic). Some MBIST tools automate the entire process of inserting the MBIST controller logic into the design as well as the interface circuitry between the controller and all memories located anywhere in the design hierarchy.

Most memory BIST solutions now support some form of BISR (built-in self-repair). Having the ability to repair embedded memories by swapping out defective rows or columns is increasingly important to achieve adequate yield levels as the size of embedded memories shrinks and their and densities continue to grow. A typical self-repair architecture consists of a fuse array to store repair information, a repair register placed next to each repairable memory for locally storing the necessary repair data, and a fuse controller for transferring data between the fuse array and each of the repair registers. All of the repair registers throughout the chip are typically placed on a serial chain in order to minimise routing. When the device is powered up, the fuse controller reads the repair info from the fuse array and scans it into all of the repair registers. This technique can be applied in the field, as well as during production test.

BIST for low-power devices
The persistent growth of mobile computing is driving an increasing need to manage power consumption within semiconductor devices. Low-power requirements affect test in two ways. First, you need to ensure that any functional power constraints are met during test execution. Second, the test solution must be compatible with whatever low-power design techniques are being used.

The first requirement has generally meant ensuring circuit switching activity levels are held below a defined threshold during test pattern application. This is accomplished by generating the test patterns in such a way as to control the number of 1 to 0 and 0 to 1 transitions within each pattern. The transition frequency corresponds directly to circuit toggle activity and thus to average power. Controlling the number of transitions is relatively straightforward for deterministically generated patterns. In the case of LBIST however, because patterns are generated on-chip using a PRPG, controlling the number of transitions within each pattern is more complicated. Some form of processing of the pattern data generated by the PRPG is therefore required.

One approach is illustrated in figure 4. Each PRPG output produces a stream of pseudo-random bits. These bit streams are fed into a phase shifter to produce a much larger number of pseudo-random bit streams to feed each of the individual scan chains within the circuit under test. To reduce the inherent toggle rate of each bit stream, a holding register is placed between each PRPG output and the phase shifter. A low-power LBIST module individually controls each of these holding registers. This module accepts a target transition frequency as input, and based on probabilistic techniques, periodically forces each of the holding registers to maintain its current value for a certain number of cycles. This produces bit streams that together produce an average transition frequency over the entire circuit under test equal to the desired target.