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DFT boot camp, Part 4: Built-in self-test

Posted: 06 Jan 2016     Print Version  Bookmark and Share

Keywords:Logic built-in self-test  LBIST 

Logic built-in self-test (LBIST) is a mechanism that lets an IC test the integrity of its own digital logic structures. LBIST operates by stimulating the logic-based operations of the IC and then detecting if the logic behaved as intended. The main advantage of LBIST is that it provides test capability without an external tester. In particular, safety-critical designs need to be tested and retested in a system or board.

To initiate testing, an LBIST engine inside the chip requires only an access mechanism like a TAP (test access port). When a device is powered on, LBIST can also check that the logic is working properly before starting any functional tests. LBIST also decreases test cost by shortening test-cycle duration and by reducing the complexity of the test/probe setup, since the number of I/O signals that must be driven and examined under tester control is usually smaller.

LBIST implementation
LBIST can have many implementations, but most depend on generating pseudo-random patterns as stimulus for the logic. The response to this stimulus is captured in a MISR (Multiple Input Shift Register). If all the registers that hold state in an IC are on one or more internal scan chains, then the registers and the combinational logic between them can be used to generate a unique CRC (cyclic redundancy check) signature over a large enough sample of random inputs. The IC stores the expected CRC signature and tests for it after collecting a large enough pattern set from a PRPG (pseudo-random pattern generator). The result of the CRC comparison with the expected signature is typically accessed via a test port based on the JTAG IEEE 1149.1 standard. The CRC signature is unique in the sense that a defect-free DUT (device under test) always generates the same signature value at the end of the test process, and each failure in the device will lead to a different signature value.

The most popular LBIST architecture is called the STUMPS (Self-Test Using a MISR and Parallel Shift register sequence generator) (figure 1). Test inputs are generated by a PRPG combined with a phase-shifter circuit. The output response analysis block includes the MISR and a signature analyser. LBIST schemes based on the STUMPS architecture can generate test stimuli and analyse test responses with little or no help from external ATE (automatic test equipment). Patterns generated by the PRPG are applied to multiple scan chains in parallel and the output (test responses) of the scan chains are compacted into a signature by the MISR (see Part 1 of this series for a description of scan chains). Any corruption in the output signature indicates a defect in the device.

Figure 1: A typical Logic BIST architecture.

One PRPG method is to use an LFSR (linear feedback shift register) to generate pseudo-random patterns (figure 2). LBIST typically requires a sequence of 50K to 100K tests to obtain high fault coverage, but the LFSR method uses very little hardware and is consequently one of the preferred LBIST pattern generation methods.

Figure 2: A third degree standard LFSR.

You can improve on this basic approach by using an LFSR for the primary test mode. Some faults can be missed by the LFSR patterns, so to increase stuck-fault coverage to near 100%, you can generate test-patterns with an ATPG program. A typical LBIST controller includes the critical functions shown in the table.

Table: LBIST Controller Features

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