DFT boot camp, Part 3: Advanced fault models

The leakage defects can be analysed by placing a resistor across the gates (from drain to source) of each of the transistor's three fins as shown in figure 5. During the cell-aware characterisation process, analogue simulation is performed with varying resistive values for all resistors for all FinFETs in a given library cell. Exhaustive analogue simulation must be performed for both single-cycle and dual-cycle tests, as many of these resistive defects will only result in small extra delays to the transistor's response and the output of the cell (figure 5).

The drive-strength defects can be analysed by placing a resistor between the drain and each of the fin's gates and between the source and the fin's gates as shown in figure 6. As with leakage defects, analogue simulation is performed with varying resistive values for each of the resistors. Once again, both single and dual cycle tests must be simulated to detect delay-related effects.

Figure 5: Leakage defect simulation.

Figure 6: Drive-strength defect simulation.

Any additional defect types that are discovered and are relevant to FinFETs can be handled in a similar fashion. The generic approach to analogue defect simulation used by the cell-aware methodology makes this straightforward.

Once the cell library characterisation is completed, the result is a UDFM model that can be used with the ATPG tool. After reading the UDFM file, the ATPG cell-aware pattern creation process proceeds similar to any of the other fault models.

About the author
Bruce Swanson is a Technical Marketing Engineer in the Silicon Test Solutions division at Mentor Graphics. He has over 20 years of experience in EDA and computer hardware design and has written numerous technical articles and conference papers. Bruce received an MS in applied information management from the University of Oregon and a BS in computer engineering from North Dakota State University.

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