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DFT boot camp, Part 3: Advanced fault models

Posted: 05 Jan 2016     Print Version  Bookmark and Share

Keywords:Automatic test pattern generation  ATPG  IDDQ  CMOS  test compression 

A recent approach, called cell-aware test, targets specific shorts, opens, and other physical defects internal to each cell by modelling it at the transistor level. Analogue simulations are performed to characterise the effects of potential short and open defects. Based on the analogue simulation results, a cell-aware fault model is created that directs ATPG to generate patterns targeting these internal cell defects. There have been multiple studies that show that tests generated using cell-aware UDFM find defects that the normal test methods miss. One such study by AMD found that after 400,000 die had been tested, 880 defective die per million passed the standard manufacturing test, but were detected by the cell-aware tests.

The first step in the cell-aware methodology is to characterise each cell in a technology library. The flow is illustrated in figure 3. The transistor layout for each cell, typically in GDSII format, is the starting point. An extraction tool, such as Calibre xRC, is used to extract a transistor-level analogue netlist, including parasitic capacitors and resistors. The netlist is used to identify the location of possible bridge and open defects. To model a potential cell internal bridge, the parasitic capacitor is replaced by a resistor model. Opens occur when there is a gap in a connection. In this case, a parasitic resistor that describes connectivity is replaced by a high-impedance resistor.

Figure 3: The cell-aware library characterisation flow produces a cell-aware fault model.

Analogue simulation is then performed to generate the cell-aware model. The analogue simulation process iteratively modifies each parasitic element in the netlist, performs the simulation, and compares the results to the fault-free analogue simulation to conclude if the inserted defect is detected or not. Defects are determined as "detected" when the cell's output voltage deviates from the "good circuit" voltage by a specified percentage (typically 50%). Not all bridge or open defects are, however, detected by a static change in the output voltage. Some may result in a delay in the output voltage swing. For these defects, a dual-cycle analogue fault simulation is performed at-speed in order to detect even small delays.

The final process in cell-aware characterisation is to convert the list of input combinations into a set of the necessary input values for each fault within each cell. Because this fault information is defined at the cell inputs as logic values, it is basically a logic fault model representation of the analogue defect simulation. This set of stimulus for each cell represents the cell-aware fault model file for ATPG.

Within this file, a simulated defect (now a fault) can have one or more input combinations. An example of a cell-aware fault model is shown here:

udfm1.0 {
udfmtype "my_stuck_at" {

cell "XOR2" {
Fault "my_stuck_01" {
Test { StaticFault "Z"=0; Condition "A"=0; Condition "B"=1; }
Test { StaticFault "Z"=0; Condition "A"=1; Condition "B"=0; }
Test { StaticFault "Z"=1; Condition "A"=0; Condition "B"=0; }

For this example fault 'my_stuck_01', ATPG will try to find any of the three input combinations when targeting this fault in a design. If any one of the combinations can be applied to an instance of the cell and the fault effect can be propagated to an observation point, then the fault is marked as detected for this instance; the other combinations are no longer necessary.

Because the cell characterisation process is performed for all cells within a technology library, any design using that technology can read in the same cell-aware fault model file. Characterisation only needs to occur once, and can then be applied to any design using that technology node library.

Modelling FinFET defects
The cell-aware methodology is well suited for addressing defect mechanisms specific to FinFETs. Consider a FinFET transistor with three fins, as illustrated in figure 4. Research suggests that two defect types should be considered for such transistors: leakage defects that force the transistor partially or completely on, and drive-strength defects that force the transistor partially or completely off.

Figure 4: A three-fin FinFET transistor.

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