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DFT boot camp, Part 3: Advanced fault models

Posted: 05 Jan 2016     Print Version  Bookmark and Share

Keywords:Automatic test pattern generation  ATPG  IDDQ  CMOS  test compression 

As an example, the test results on one 90 nm CMOS design demonstrated that embedded multi-detect tests detect 2.3% to 4.7% more defective devices than conventional single-detect stuck-at tests. This fault model or detection method is becoming more common because it doesn't increase the size of the test set and can produce additional detection.

Deterministic bridging
The deterministic bridging test utilises a combination of layout extraction tools and ATPG. Based on a set of geometric rules, the extraction tool creates a list of net pairs that have the potential of bridging (figure 1). This list is then fault simulated using existing stuck-at and transition patterns to determine which bridge defects can be detected. The net pairs that are not covered by the initial patterns are identified, and then used by the ATPG tool to generate a specific set of test patterns to completely validate that the remaining nets are not bridged.

Figure 1: These examples of geometric rules help you identify potential bridges.

Small-delay defects
At design nodes of 180 nm and larger, the majority of manufacturing defects are caused by random particles that cause bridges or opens. There are very few timing related defects at these larger design nodes because manufacturing process variations cause relatively small parametric changes that would affect the design timing. At design nodes of 90 nm and smaller, however, the same manufacturing process variations can cause on-chip parametric variations to be greater than 50%. This creates a situation where timing-related failures are a significant percentage of overall test failures.

You might expect that transition test patterns, covered in Part 1 of this series, would find all of the timing defects in the design. Most or the time, it will, but some of the smallest delay defects can evade the basic transition test pattern. For example, when a path through vias, gates, and interconnects has a minor resistive open or other parametric issue that causes a delay, the accumulative defect behaviour may only be manifested by long paths. A common scenario is where the same via type is used multiple times in the same path, and the vias are formed as resistive vias (figure 2).

Figure 2: Resistive opens can introduce small timing delays that can cause ICs to fail tests.

To detect this defect, an SDD (small delay defect) test can be performed. Circuit timing and physical layout information is used to guide the test generator to detect faults through the longest paths to improve the ability to detect SDDs. SDD testing is often referred to as timing-aware ATPG and is growing in usage for designs that have tight timing margins and low DPM (defect-per-million) requirements. The resulting patterns have a much higher probability of catching small-delay defects. One case study of a low DPM product has shown a 50% reduction in test escapes when timing-aware ATPG was applied.

User Defined Fault Models
UDFM provides users the ability to define new fault models without waiting for them to be built into their commercial test tools. It allows users to define the stimulus requirements that must be met in order for test patterns to detect a specific defect. The UDFM model is text based and incorporates the standard fault models provided with ATPG tools. Here's an example of a UDFM:

Cell "MUX2" {
Fault "Z1" {
test { StaticFault "Z"=1;Condition "D0"=0,"D1"=0,"S"=0;}
test { StaticFault "Z"=1;Condition "D0"=0,"D1"=1,"S"=0;}
test { StaticFault "Z"=1;Condition "D0"=0,"D1"=0,"S"=1;}

This UDFM specifies that ATPG must produce one of the three listed input patterns in order to detect fault Z1. This fault model provides a lot of flexibility and can specify any number of test cycles and can utilise library models, instances, and hierarchical paths within the design.

Cell-aware test
As the industry moves to increasingly smaller geometries, we have discovered that fault models and associated test patterns are becoming less effective for ensuring desired quality levels. All of the existing fault models only consider faults on cell inputs and outputs, and on the interconnect lines between these cells. It turns out, however, that a growing number of defects occur within the cell structures. With more recent fabrication technologies, the population of defects occurring within cells is significant—as much 50% of all defects. In addition, the performance advantages of FinFETs have led to widespread adoption of these new transistors at advanced technology nodes. Consequently, we need a way to generate test patterns that efficiently target potential new defects at the transistor level.

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