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DFT boot camp, Part 3: Advanced fault models

Posted: 05 Jan 2016     Print Version  Bookmark and Share

Keywords:Automatic test pattern generation  ATPG  IDDQ  CMOS  test compression 

The notion of a fault model, that is, the expected behaviour (response) of a circuit when a defect is present, serves as basis for modern semiconductor testing. Automatic test pattern generation (ATPG) tools use fault models to find the patterns required to detect the presence of defects at all points in the circuit. In Part 1 of this series we described the most basic fault models and associated tests: the "stuck-at" and "transition" fault models. In this article, we cover a number of more advanced fault models that are commonly used in conjunction with scan testing.

The IDDQ test relies on measuring the supply current (IDD) of an IC's quiescent state, when the circuit isn't switching and inputs are held at static values. Test patterns are used to place the device under test in a variety of selected states. By performing current measurements at each of these static states, the presence of defects that draw excess current can be detected. The value of IDDQ testing is that many types of faults can be detected with very few patterns. The drawback is the additional test time to perform the current measurements.

Toggle fault testing ensures that a node can be driven to both a logic 0 and a logic 1 value, and indicates the extent of your control over circuit nodes. Because the toggle fault model is faster and requires less overhead to run than stuck-at fault testing, you can experiment with different circuit configurations and get a quick indication of how much control you have over your circuit nodes. Because the toggle fault model only excites fault sites and does not propagate the responses to capture points, you can't use it for defect detection. This fault model is sometimes used for burn-in testing to cause high activity in the circuit.

N-Detect and EMD
The basic idea of n-detect (or multi-detect) is to randomly target each fault multiple times. The way the fault is targeted is changed randomly, as is the fill (bits that don't matter in terms of the fault being targeted) in the pattern set. This approach starts with a standard stuck-at or transition pattern set targeting each potential defect in the design. The pattern set is analysed to see which potential defects are addressed by more than one pattern in the total pattern set. Then, additional (different) patterns are generated that specifically target the defects detected fewer times than the user-specified minimum. The combined information for all the resulting patterns increases the potential for detecting a bridge defect that might otherwise escape.

EMD (Embedded multiple detect) is a method of improving multiple detections of a pattern set without increasing the number of patterns within that pattern set. EMD uses the otherwise unspecified—fill or don't care—bits of an ATPG pattern to test for nodes that haven't reached their N-detect target. Standard multiple detect (N-detect) will have a cost of additional patterns but will also have a higher multiple detection rate than EMD. How much difference there is between EMD and multiple detect defect detection will depend on the particular design's pattern set and the level of test compression used.

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