Design level-shifter with low power dissipation
Keywords:SoCs level-shifters inverters dissipation power consumption
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Figure 1: Conventional level shifter. |
The conventional architecture involves a cascade of two inverters (p2/n2 and p3/n3), with OUT coupled to the transistor (p4) above first inverter. The transistor p4 helps to decrease/increase the effective drive strength of transistor combination (p2—p4), during the transition of input (IN) from low-to-high/high-to-low. An additional NMOS diode is also added in parallel to transistor p4 to enable the switching of first-inverter output from low-to-high when IN goes from high-to-low.
The problem here is that the addition of always-on NMOS results in static current flowing through the first inverter configuration (from VDD to GND through n1, p2 and n2), when the input is at logic 1 (VDDL).
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Figure 2: Direct current path in half cycle. |
Moreover, this also results in the output of first inverter (INT) being at weak 0 (i.e., not all the way to ground) which could result in power consumption in the second inverter (p3-n3).
Proposed level shifter
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Figure 3: Proposed Level Shifter Circuit. |
The proposed architecture is similar to the conventional architecture since it is also a cascade of two inverters (M1-M2 and M6-M7) with the output of second inverter (M6-M7) controlling the effective drive-strength of PMOS (M4, M2) of first inverter.
The inclusion of transistor M3 (with its gate connected to inverted version of IN (IN_B)) results in fast turn-off of current through M2-M3-M4 when IN goes from low-to-high, thus resulting in fast transition of node A from high-to-low, which in turn gives an improvement in speed.
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