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Realistic approach to fixing X-pessimism

Posted: 21 Dec 2015     Print Version  Bookmark and Share

Keywords:RTL  simulation  gate-level simulator  X-pessimism  MUX 

Nowadays digital designs are coded with RTL descriptions for fast simulation and then are synthesised to a gate-level description. Ideally, gate-level simulations match the behaviour seen at the RTL stage. Unfortunately, X-pessimism happens in gate-level simulations and causes mismatches with RTL simulation. Resolving these differences has been a chronic problem for digital designers for more than 20 years.

A gate-level simulator is pessimistic in that it shows that a signal does not resolve to a known logic value (0 or 1), but in the real hardware a signal will always resolve to a known value.

Let take a look at a simple example that illustrates the problem.

Here we see a two-input MUX that has a Select signal (Sel) and two data inputs. If the Select signal is an X value, the output will be an X. If the data inputs both have the same value (0 or 1) the output of the MUX will be the corresponding 0 or 1. In simulation, however, the output will be an X if both data inputs have the value of 1. The simulator is showing pessimistic behaviour compared to real hardware.

This pessimism requires the engineer to trace back the signal to find the functional error that causes the simulation to differ from the RTL behaviour. Resolving the issue can be very time-consuming and is largely a manual process. Correcting this pessimism is also error-prone. Errors can occur when tracing back in time, because a decision must be made whether the X value is the result of pessimism or instead is the propagation of an X signal. That X signal may be caused by RTL behaviour and be due to X-optimism in the design.

At the gate-level, pessimism is fixed by forcing the signal to a known value, but forcing just any X-value in the design would be incorrect. Only those signals that arise from pessimism should be forced to a known value.

In doing manual traceback of X-signals, SoC design teams have found that months of time are needed to fix their gate-level simulations to match their RTL simulations. They also have experienced fear that they might have missed something in the design, because the netlist view of their logic is unfamiliar to them. Finding the right point in design and the correct value to be forced at that timepoint is difficult. And this leads to constant worry and sleepless nights.

There are workarounds that design teams use, but risks are involved. One method is to do random initialisation of all uninitialized flip-flops. This, in essence, removes the X values from the design. However, this approach can mask bugs. For example, if one of those X-optimism bugs made it into gate-level simulation and the X value has been removed, the bug will not be discovered; it can slip through to implementation and possible failure in the field. And when design teams randomly initialize, they are not going to match the behaviour of the real hardware, because hardware could take a different value. So there is a big risk in random initialisation.

Another approach to eliminating all X's is to add a reset to all memory elements. This method eliminates the most common source of X's—uninitialized flops. However, synchronous resets sometimes can cause pessimism issues to be introduced during the synthesis process. Also, other sources of X's do exist in a design, such as explicit X-assigns for flagging illegal states, bus contention, and out-of-range references. A more significant issue is that extra resets eat into power, size, and routing budgets. Resettable flops are larger, more power-hungry, and require additional routing resources. Resetting all flops is practical only for smaller designs, and does not address all X-sources.

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