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Understanding graphics memory needs of wearables

Posted: 08 Dec 2015     Print Version  Bookmark and Share

Keywords:Internet of Things  IoT  embedded RAMs 

A closer inspection of the specs of the latest generation computer Graphic Processing Units (GPUs) from Nvidia and AMD shows a significantly higher memory, often in Gigabytes. This is because most modern GPUs are built for gaming & HD rendering, with a host of extra features that suck up memory space – MSAA (which multiplies the size of buffer by sampling frequency), pre-fetching, shadow buffers, deferred rendering and special effects. Even features we take for granted, like windowed scrolling, require additional buffer space. Most gaming buffers use triple buffering (which translates to 3 buffers for every frame) and HDR (usual HDR depth is 64 bits, instead of 24). Many of these high-end GPUs also support multiple high-definition displays, which means a dedicated internal buffer for each of those displays.

However this host of features isn't yet required for most wearable and portable devices, due to their smaller displays. The ideal approach is to use the MCU's embedded memory resources as a frame buffer. This has the highest throughput and is the simplest to implement. But most MCUs come shipped with insufficient memory for the latest generation displays in wearables. Moreover, increasing program complexity necessitates greater embedded memory to be used as the MCU's L1 cache. For the most current generation wearable devices, display resolution is QVGA (Quarter Video Graphics Array), and for such displays the following specifications will suffice – 24-bit | 480*360 | 30fps. This translates to a pixel per inch (ppi) of 300 for wearable sized displays. The memory requirement for such a display is 4Mb with a throughput 120 Mbps. However, future devices will have significantly higher resolution displays, crossing a ppi of 400, like many of the latest generation cell phones. Increasing ppi for displays of the same size means the frame buffer size increases accordingly. As explained earlier there are two ways of implementing a frame buffer of this size: a 4Mb buffer of ~120 Mbps throughput or 16Mb buffer of ~30Mbps throughput. Among the two alternatives, the small buffer option has manifold benefits – smaller footprint (in case of die or CSP), lower power consumption, lower cost, and more options (as you go up the density ladder the number of manufacturers and variants decreases). With wearables, footprint, power consumption, and cost are often the most important deciding criteria for any device component.

The most widely used memory for frame buffering is dynamic RAM (DRAM), despite the fact that the highest performance widely available memory today is static RAM (SRAM). DRAMs have higher power consumption and lower throughput than SRAMs. Even though they have better performance, which is ideal for latest generation high performance portable devices, SRAMs aren't used in most portable battery-backed devices. This is because of a smaller portfolio – SRAMs are only available in low-density options, peaking at 128Mb. An SRAM has a more complex memory cell structure comprising of 6 transistors, vs. 1 transistor + 1 capacitor for a DRAM. That is why SRAMs are restricted from moving to higher densities, which has proved to be its biggest limitation. Though this limitation has prevented SRAMs from being used in legacy consumer devices (PCs, televisions, cell phones, etc), it isn't as much a deal breaker for wearable devices, given the smaller memory size required for frame buffering. Furthermore, the higher performance (higher throughput equals lower power) is an advantage in favor of SRAMs in these devices.

SRAMs, once considered a defunct memory type, look set to make a return thanks to renewed need for high performance, especially low power consumption.Many leading SRAM manufacturers have come out with a slew of innovations to especially cater to the demand from wearable systems – from higher reliability to newer packages.

About the author
Reuben George works with the Memory Products Division at Cypress Semiconductor in Product Marketing. He holds a BE in Electrical& Electronics Engineering from the Birla Institute of Technology and Science (BITS), Pilani, in Rajasthan, India.

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