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Design tools boost productivity for All Programmable systems

Posted: 03 Dec 2015     Print Version  Bookmark and Share

Keywords:Xilinx  All Programmable SoC  FPGA  design suite  ADAS 

Xilinx Inc. has rolled out its Vivado Design Suite HLx editions that promise to elevate the level of productivity for designing All Programmable SoCs, FPGAs and the development of reusable platforms. When used together with the UltraFast High-Level Productivity Design Methodology Guide from the company, users can realise 10 to 15 times productivity gain over traditional approaches, added Xilinx.

To enable high productivity flows, the HLx editions include HL System edition, HL Design edition and HL WebPACK edition. All HLx editions include Vivado High-Level Synthesis (HLS) including C/C++ libraries, Vivado IP Integrator (IPI), LogicCORE IP subsystems and the full Vivado implementation tool suite to enable mainstream users to readily adopt the most productive and advanced C and IP-based design flows, stated the company. In addition, Xilinx and its Alliance ecosystem are continuously expanding market-specific C libraries such as OpenCV for video and image processing and machine learning for automotive driver assistance systems (ADAS) and data centre applications.

Xilinx's LogiCORE IP subsystems are highly configurable, market-tailored building blocks that integrate up to 80 individual IP cores, software drivers, design examples and test benches, touted the company. New IP subsystems are available for Ethernet, PCIe, video processing, image sensor processing and OTN development. These IP subsystems are based on industry standards such as AMBA AXI 4 interconnect protocol, IEEE P1735 encryption and IP-XACT to enable interoperability with Xilinx and Alliance member IP and to accelerate integration.

The combination of C-based IP and pre-packaged IP subsystems are rapidly combined leveraging Vivado IP Integrator for integration automation. Vivado IPI's integration automation provides a device and platform aware, interactive environment that supports intelligent auto-connection of key IP interfaces, one-click IP subsystem generation, real-time DRCs and interface change propagation, combined with a powerful debug capability. The platform aware intelligence, can preconfigure the Zynq SoCs and MPSoCs processing system with the correct peripherals, drivers, and memory map to support the target board. Design teams can now rapidly identify, reuse and integrate both software and hardware IP, targeting the ARM processing systems and high-performance FPGA logic.

HLx claims to speed the creation, modification and programming of All Programmable platforms for hardware engineers, complementing the Xilinx SDx development environments (SDSoC, SDAccel and SDNet) that are tailored for software and systems engineers. The SDx family of development environments enable software-defined programming of HLx generated platforms using a mix of C, C++, OpenCL and the emerging P4 language for packet processing. HLx and SDx are Xilinx's design enablement solutions for developing smarter, connected and differentiated systems for All Programmable devices including Zynq SoCs, MPSoCs, ASIC-class FPGAs and 3D ICs, said the company.

The Vivado Design Suite HLx editions upgrades are available in the Vivado Design Suite 2015.4 release supporting Xilinx 7 series, UltraScale and UltraScale+ devices. The HLx edition is available as a no-cost upgrade to the Vivado Design Suite.

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