Perform thermal analysis of PCB mounted SOP(2)

For the CFD simulation, the test board we used was a six-layer board, with dimensions of 59 x 61 mm. We assumed that the copper coverage for each of the conducting layers was smeared uniformly within the layer's volume. Based on this, we calculated the thermal conductivity (k) of each layer as a volume average based on the per cent of copper coverage within an individual layer (table 1). For further accuracy, we could also have processed the images for copper coverage within a layer to provide a conductivity mapping within the plane of the board.^[2]

We recommend discretely modelling each of the conducting layers with orthotropic conductivity for the entire thickness of the board to accurately predict the value of the junction temperature. Modelling the layers discretely, rather than with a lumped model, captures the effect of heat spreading within the board more accurately for various heat-transfer paths.

Table 1: Board stack-up and per cent of copper coverage.

Thermal simulation without a heatsink
We conducted the first set of simulations to study the thermal behaviour of the PSOP mounted on the primary side of the board where the copper slug was soldered to the board. We kept the board horizontal with respect to gravity in an ambient temperature of 85°C.

To emulate real working conditions, we applied heat to two-thirds of the top of the die. In the simulation, the junction temperature (T_j) was measured at the geometric centroid of this area, and case temperature (T_c) was measured at a point in the copper slug just above the soldered interface (figure 2). It is possible to also monitor the temperature of the leads, plastic surface, or any given position to validate the computational results with available test data.

Figure 2: Temperature measurement locations.

We added thermal vias under the slug to provide a more conductive path from the copper slug into the board. The vias were placed right under the copper slug because our numerical investigations revealed a small advantage of adding vias beyond the slug area. This also helps in lowering the manufacturing cost of the board.

We investigated two possible scenarios for thermal vias: one where the inner layers were isolated, and a second where the inner layers were stitched together. Stitching the inner layers lowers the junction temperature because a fraction of the heat entering the slug can spread in inner layers; however, including the inner layers raises the core body temperature of the board. So depending on the application, the inner layers could be isolated or used for thermal management. In this study, the secondary side of the board was completely covered with copper.

Figure 3 shows the temperature plots for the package in still air at 85°C and thermal power P = 2 W with die-attach material of k = 1.6 W/mK [watts per metre kelvin]). We replaced the die-attach with the more conductive material, k = 50 W/mK, which significantly reduced the junction-to-case thermal resistance (θ_jc) of the package from 6.61°C/W (celsius per Watt) to 1.12°C/W.

Figure 3: Temperature plots for the package in still air at 85°C.

Thermal simulation with a heatsink
We soldered a heatsink to the back side of the board to increase the power dissipation through the package, using thermal grease between the board and heatsink. Adding the heatsink significantly reduced the junction-to-ambient thermal resistance (θ_ja) from 16°C/W to 5.73°C/W. Heat-flux plots for a plane cutting through the package show the heat spreading over a larger surface area hence reducing the junction temperature for a given value of thermal power (figure 4).