Using SAR, sigma delta converters for multiplexed DAS

Multiplexed data acquisition systems (DAS) used in industrial process control, portable medical devices and optical transceivers need increased channel density, where the user wants to measure the signals from multiple sensors and monitor and scan many input channels in to a single or several ADCs. The overall benefit of multiplexing is fewer number of ADCs per channel required, saving print circuit board (PCB) space, power and cost. Some systems in automated test equipment and power-line monitoring applications demand dedicated track and hold amplifier and ADC on per channel basis for simultaneously sampling the inputs to obtain increased sampling rate per channel and to preserve the phase information at the expense of additional PCB area and power.

System designers make trade-offs based on performance, power, space, and cost requirements in their end application. They select one of the converter architectures and topologies and implement their signal chain using either discrete or integrated components available in the market. Figure 1 shows a simplified block diagram of multiplexed DAS that monitor and sequentially sample various sensor types. Sometimes signal chains utilise either buffer amplifier or programmable gain amplifier between the multiplexer and ADC.

A small voltage glitch or kickback occurs at the multiplexer input when it switches channels. This kickback is a function of the turn-on and turn-off times, on-resistance, and load capacitance of the multiplexer. Large switches with low on-resistance typically result in a large output capacitance that must be charged to a new voltage each time the input is switched. If the output doesn't settle to a new voltage, crosstalk error will occur. Therefore, the multiplexer's bandwidth must be sufficient and a buffer amplifier or large capacitors must be used at the multiplexer input to settle a full-scale step. In addition, the leakage current flowing through the on-resistance will introduce a gain error, so both should be kept small.

SAR vs Σ-Δ ADC architectureFigure 2 shows the basic converter architecture of successive-approximation register (SAR) based on the charge redistribution capacitor digital to analogue converter (DAC) array. It samples input signal once at each convert start edge, compares bit on each clock edge, adjusts output of the digital to analogue (DAC) converter, through control logic until that output very closely matches the analogue input, so it requires N-number of clock cycles from an independent external clock to implement a single N-bit conversion in an iterative manner.