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Cadence rolls out latest enterprise emulation platform

Posted: 19 Nov 2015     Print Version  Bookmark and Share

Keywords:Cadence Design Systems  emulation platform  verification  SoC  ASIC 

Cadence Design Systems has developed the Palladium Z1 enterprise emulation platform as part of the company's system development suite, which includes platforms for concurrent hardware/software design and verification. The solution aims to support global design teams who need to verify increasingly complex SoCs, and claims to deliver, on average, 2.5X better workload efficiency than the closest competitor, stated Cadence.

The platform promises to deliver enterprise-level reliability and scalability, with 5X greater emulation throughput; better resource utilisation via advanced virtual target relocation and job re-shaping capabilities; and 92 per cent smaller footprint via rack-based blade architecture.

Verification has become the biggest challenge in SoC development. However, traditional verification tools haven't kept pace with how quickly SoC and ASIC design size and complexity are growing. Simulators slow to a grind as RTL and gate design size increase. This, in turn, delays system integration and extends the overall verification cycle.

Palladium Z1

Palladium Z1

The Palladium Z1 platform bridges the verification productivity gap to accelerate verification of SoCs, subsystems, and IP blocks, as well as system-level validation. Easy to manage and scale, the platform: compiles databases for different workloads, with up to 140MG per hour compile times on a single workstation; allocates as many workloads as possible; runs workloads based on priorities; and debugs for both pre- and post-silicon bugs.

Smart emulation resource utilisation

The way that the Palladium Z1 platform manages emulation resources can save you time and effort. The platform's unique virtual target relocation capability, along with advanced job shaping allocation, avoids recompiles by allowing payloads to be allocated into available resources at runtime. The platform can execute up to 2304 parallel jobs with four million gate granularity and scales to 9.2 billion gates.

Compared to the Palladium XP II environment, the platform offers an up to 44 per cent reduction in power density, along with a reduction in power consumption per emulation cycle by a factor of three or more, noted the company.

Its rack-based blade architecture results in a 92 per cent smaller footprint and 8X better gate density, compared to the Palladium XP II platform. The Palladium Z1 processor-based compute engine is also designed with massive parallelism, delivering 4X better user granularity than its nearest competitor.

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