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Accelerate digital IP design with formal verification

Posted: 26 Nov 2015     Print Version  Bookmark and Share

Keywords:verification  digital IP  RTL  Universal Verification Methodology  System Verilog 

It is apparent that the task of verification looms large in the design of digital IP, as well as the design of SoCs. The target is to reach 100% for both RTL code and functional coverage, minimising the time spent obtaining it. The most widely used methodology is based on Universal Verification Methodology (UVM) random constrained tests (either System Verilog or e language) that permit the construction of complex tests in a relatively short time while stressing the RTL code and keeping track of functional coverage. Some verification engineers also use formal methodology for verifying a dedicated part of the block such as standard interfaces, which completes the verification of the IP.

This article will describe a different approach for digital IP verification based on formal methodology, exhaustively verifying the functionalities through the definition of properties. The formal approach has the advantage of avoiding development of test benches. This new flow has been used during the design of a digital IP and has proven to significantly shrink verification time.

Common verification flow
Currently, the most commonly used flow for the verification of digital IP and System on Chip (SoC) is based on UVM through the use of Verification Components (VC) that are available from third parties or developed from scratch when non-standard protocols are used. The test bench is then completed with scoreboards for self-data checking, assertions for verifying specific parts of the design, and covers for tracing functional covers. In the last few years, Formal Verification has begun to be used in the verification flow for both SoC and IP. In the SoC, Formal Verification has become quite common in the verification of connectivity between SoC peripherals' and pads, mainly when the muxing scheme is formed by several peripherals connected to a reduced number of pads, which increases the combination that needs to be verified. Sometimes, in IP verification, the Formal methodology is used for checking the bus protocol interface and register access policy.

Now, focusing on the verification of digital IP, we can summarise the flow as the one depicted in figure 1. When the first version of RTL is ready, the first step of a good verification flow starts with the definition of verification and test plan. In this phase, we are going to define the functionalities that we want to check and the skeleton of the tests.

The next step is to develop the UVM test bench; custom UVM blocks are built for checking the specific IP functionalities, while third party UVM VC are instantiated and bound on RTL.

At this point, we can develop UVM tests according to the verification plan. The first thing that every verification engineer needs to keep in mind is that the tests must be self-checking; any points listed in the verification plan must be checked automatically by using scoreboards, checkers, and assertions. Then, the extensive use of coverage structures permits the quantification of how good the tests are.

Figure 1: Common verification flow of digital IP.

Occasionally, this flow could include the Formal Verification. At a certain point of the task, someone might decide to check specific blocks of the IP such as the bus protocol interface by using Assertion-Based Verification IP (ABVIP) and precise functions implemented through Finite State Machine (FSM) by writing assertions.

As we know, the verification task is an iterative process with two main loopbacks: RTL Bug Fix and Functional and Code Coverage.

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