Global Sources
EE Times-India
 
EE Times-India > EDA/IP
 
 
EDA/IP  

Addressing SoC PDN challenges

Posted: 24 Nov 2015     Print Version  Bookmark and Share

Keywords:Power Delivery Network  PDN  partitioning  power gating  DRC 

The Power Delivery Network (PDN) is the one of the most critical components in an SoC as it supplies power to all the components in the design. With increasing complexity of designs, the partitioning approach is gaining popularity, and power gating helps reduce rising consumption. With these approaches, designs become more efficient, but they introduce additional issues and challenges with respect to the design of the PDN.

In this paper we will introduce the usual flow taken in the design of the power grid. This will be followed by the challenges and issues faced while designing the PDN in multi-partition and low-power designs.

Power grid design
Metals used in the power grid mostly depend on the power requirement of the design and the metal options used in the technology node. More metal options cost more but it creates more robust design than a less metal option design. Metal usage (width, spacing, and metal stack) in the power grid is defined by the power requirement. If we have more power requirement, then in this case we must use metal stripes of more width for the grid.

Metal width should be chosen such that no routing track is wasted. Sometimes DRC rules also play a role in deciding the power grid metal width. Let's have a look on the DRC spacing sample table which is given below.

DRC spacing rule depends on the metal width & also on the parallel run length of the metal. Below spacing table shows that how spacing varies with metal width used. If we take M4 power stripe width of w2µm, then in this case spacing from the next M4 signal route of width w1µm (minimum metal width of M4) must be of "s3". M4 width "w2" is chosen to take-care of the wide metal rule so that we don't waste the nearby routing track. We are assuming routing grid is of "x"µm for a particular technology node which may vary from technology to technology.

Challenges of power grid design and analogue integration
Power gating in partitioned designs: Partitioning the design helps in breaking the design into smaller hierarchies which can be handled in a more effective manner individually. Also power gating some of these modules lead to significant reduction in total power of the design. But power gating the modules leads to break in power grid continuity. And thus one of the biggest disadvantages of power gating partitions is the IR drop issues faced by core grid. This discussion is specifically for wire-bond based packages (QFP, QFN, BGA etc).

One of the ways by which we can minimise the drop is by making the grid stronger. This needs to be done quantitatively since it has its own limitations of congestion and significant increase in die area.

The second approach can be by providing feed-through paths for core power over the power gated module so that the core grid remains continuous.

Figure 1: Traditional power grid in power gated partitioned design.

Figure 2: Introducing feed-through paths over partitions to maintain core grid continuity.


1 • 2 • 3 Next Page Last Page



Comment on "Addressing SoC PDN challenges"
Comments:  
*  You can enter [0] more charecters.
*Verify code:
 
 
Webinars

Seminars

Visit Asia Webinars to learn about the latest in technology and get practical design tips.

 

Go to top             Connect on Facebook      Follow us on Twitter      Follow us on Orkut

 
Back to Top