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Timing closure issues in multi-level partitioned SoCs

Posted: 17 Nov 2015     Print Version  Bookmark and Share

Keywords:SoC  partitioning  IP  modeling  EDA tool 

With increasing SoC design complexity, hierarchical backend design closure has become prevalent across the industry. Block and sub-block partitioning allow designers to exploit engineering and tool bandwidth more efficiently through optimized resource use. In addition, this approach is compatible with a bottom-to-top design approach.

This is in keeping with design practice wherein mature IP partitions are taken into the backend cycle while work is going on to finish the rest of the chip. Benefits like design-cycle reduction have prompted designers to push for multi-level partitioning schemes. However, as the level of hierarchical partitions increases, so do the challenges involved in their closure and signoff.

In this paper, we discuss the major timing and implementation challenges involved in multi-level hierarchical partitioning and modeling schemes.

Multi-level hierarchical partitioning and implementation
Multi-level hierarchical partitioning and implementation involves partitions which comprise of internal physical sub-partitioning. In other words, in this approach, hierarchical portioning is done on the partition itself. Consider the example of SoC partitioning schemes as shown in figure 1. Level 0 corresponds to a single flat implementation of the entire chip where the only physical interface being modeled is the one concerned with the external world (shown in blue). In other words, inside the chip, there are only logical boundaries and no physical boundaries.

Figure 1: A typical multi-level hierarchical partitioning scheme in a SoC.

The internal logic interactions (shown in black) across core, APP_SUB_SYSTEM etc. are, thus, covered inside the flat design itself. This type of scheme presents itself with minimal interface budgeting complexities (discussed in next section) concerned with inter-partition interactions as there is only a single partition. However, this scheme is not preferred for large designs mainly due to limitations of EDA tool run time, memory and machine resource requirements.

To ease such design scenarios, a designer may opt to use a single level hierarchical partitioning as shown in level 1. In this case, the designer ends up with 4 physical partitions or blocks as shown in table 1. In this approach, the design limitations in terms of engineering resources are relaxed, but inter-partition paths become more complex and need special care as far as budgeting is concerned. Comparing level 0 to level 1, we observe that while in level 0 only the external interface paths contributed towards major uncertainty, in level 1 almost all the inter-partition paths present us with the similar uncertainty and complexity of an I/O interface. However, nature of interface paths of level 1 and level 0 (external interface) are more or less similar and hence same methods and constraints can be used to model them. There is a very important difference between level 0 and level 1 interface paths. Level 0 interface paths are governed by protocols wherein some of the protocols have definite budgets given for the SoC. The SoC has to abide by these budgets only. On the other hand, for inter-block paths, the budgeting lies in the hand of the designer. There is no standard protocol governing the interactions and the budget allotment is generally iterative.

Moving towards level 2, we further divide the partitions of level 1 into smaller sub-blocks. With this, we are finally left with 7 unique physical partitions. This massively helps in reducing tool run time and resource limitations as the design has been broken into much smaller parts; but similar to level 1, the inter-partition paths & uncertainties also increase. While in the case of level 1, we are able to model the partition interface similar to the external interface of level 0; level 2 comes with a far more complex interface timing and implementation, especially if the paths involved are across multiple partitions. Moreover, the benefits of optimization are also reduced significantly as the optimization across physical boundaries will not be very effective.

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