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Design practices to ensure proper testability

Posted: 28 Oct 2015     Print Version  Bookmark and Share

Keywords:RTL  Automatic Test Pattern Generation  ATPG 

Delay between M1 & M2 (simulation): Due to interconnect delay, M2 makes a late transition than M1 resulting in a glitch at reset resetting the flop.






Figure 8c: Real simulation Scenario.

In order to solve the problem, only a single multiplexer should be used in the reset path.

Synthesis of switching logic for controlling reset: As mentioned above, a multiplexer is added before the reset of a flop. During synthesis, this multiplexer may be converted to complex gates (AOI—AND OR INVERT) as shown in figure 9(a).

Figure 9a: Synthesised mux.

This scenario may result in a glitch at the reset of the flop leading to the false output.

Figure 9b: A failing scenario.

To prevent the glitch, this multiplexer should be preserved using pragma in RTL so that the logic is synthesised as a glitch-free multiplexer instead of any random AOI combination working as a multiplexer.

Common source of inputs of combinational logic
A combinational logic (for example 2-input AND gate or a 2-input OR gate) having both its inputs driven from same source with one being inverted will maintain the same constant output value regardless of the state of the driving node, but the output will probably contain a glitch when the driving node changes state.

Figure 10: Two input AND gate with common input sources.

Combinational Loops
When the output of a combination logic is fed back to one of its input, a combination loop is formed. ATPG tool simulates the design assuming zero delay in combinational elements which may result in undetermined output for one or more input combinations.

Figure 11: Combinational Loops.

As shown above, the input combination (A, B, C) = (1, 0, 0) will create oscillations in the circuit. To prevent this, the tool breaks the loop and models it as a TIEX block in the feedback path which results in coverage loss. Therefore such loops should be avoided.

Analoue Blocks
Special handling is required for all analogue blocks during testing when working with ATPG tools. Many analogue blocks can have embedded digital logic and we should ensure that all this logic is testable. The digital inputs/outputs of the analogue block interface needs to fully controllable and observable. At the same time analogue inputs/outputs should be wrapped or safe-stated. There can be requirements based on test cases to keep analogue portion of the block in a low power state (power down or sleep), along with its analogue outputs either in high impedance state or driving a constant value, so special care needs to be taken care in such cases via safe stating of the block.

Voltage and Temperature Triggers Masking
SOC has voltage and temperature detection circuits built in them, to generate interrupts in case either goes beyond the defined specification. During testing these signals need to be disabled or masked, since there are multiple tests like Very Low Voltage (VLV) Test, High Voltage Stress Test, etc., which will start showing fails if these interrupt signals are not masked.

Figure 12: Analog Wrapper.

It is very important to make our designs DFT-friendly. The simple practices above can save much design time, effort, and frustration. Hence, it is recommended that designers ensure that all of the above design practices are followed.

About the author
Gunjot Kaur, Sidhant Goel and Mayank Parasrampuria contributed this article.

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