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Design practices to ensure proper testability

Posted: 28 Oct 2015     Print Version  Bookmark and Share

Keywords:RTL  Automatic Test Pattern Generation  ATPG 

Zero Delay (ATPG/Idle): ATPG tools while generating patterns works on a zero delay type simulation model. Data is sampled just before the clock edge, so from tool's perspective, the output is always high during pattern generation in this case.

 

 

 

 

 

 

Figure 6a: Zero Delay.

Data Skewed with respect to clock (Simulation): In simulation, due to skew in design between the data and clock we can have two scenarios, data coming either early or late and in both such cases we will start getting fails.

Figure 6b: Data Early.

Figure 6c: Data Delayed.

Reset Control
As discussed previously, clock and reset of a flop must be fully controllable. To achieve this, a multiplexer is placed in the reset path as shown below. The first input of the multiplexer is the functional reset as before. The second input is the DFT (test) controlled RESET and the select line (test mode) is used by DFT to switch to the controlled reset in test mode.

Figure 7: Reset control using mux.

Cascading of switching logic in the reset path
The select signal (Reset Override) is not timed by the timing team, so any random skew in this signal must not affect the state of any of the flops. If two or more such switching logics are cascaded as shown, this may result in a glitch to the RESET pin of the flop which will corrupt its state.

Figure 8a: Cascaded reset control logic.

Zero Delay (ATPG): Due to zero delay in ATPG, the select line M1 & M2 will toggle at the same time so the reset RST is always high.

Figure 8b: Zero Delay ATPG.


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