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Design practices to ensure proper testability

Posted: 28 Oct 2015     Print Version  Bookmark and Share

Keywords:RTL  Automatic Test Pattern Generation  ATPG 

SoC sub-components (IPs) generally come from various sources—internal and external—and with that it has become imperative that designers ensure the RTL is testable. If the RTL has testability issues, test coverage goals can't be met and the RTL needs to be modified, which means several iterations of synthesis, verification, and Automatic Test Pattern Generation (ATPG).

Here we will discuss the basic design practices to ensure proper testability.

Clock Control
For ATPG tool to generate patterns, the clock and reset of a flop must be fully controllable; i.e., the tool can trigger the clock whenever required – it must not be gated by any other uncontrollable signal.

Clocks gated by combinational logic: In case the clock is gated by a combinational logic then an override should be added using a shift/test mode signal for ensuring proper shift & capture clock propagation.

Figure 1: SHIFT_MODE = 1 during shift.

Internally generated clocks: For all internally generated clocks a bypass should be provided. In case there is a requirement of this clock, say we need PLL clock for at-speed testing, then a clock control logic should be added on them.

Figure 2: Bypassing all internally generated clock.

An example for this would be clock generated by sequential logic:

Here the clock is generated by the output of a flop, since this generated clock is not directly controllable by the ATPG tool, we need to add clock control logic.

Figure 3: Bypass for clock generate from a flop.

Test clock selection: It must be ensured that test clock frequency is always greater than or equal to the functional clock frequency, so that we never end up under-testing a logic.

Using clock as data: When clock is used as data in a design, then it must always be ensured that we use test mode signal to gate this data path (i.e., clock to the data cone). Otherwise a race condition may result that produces an inaccurate simulation results.

Figure 4: Eliminating race condition.

Un-clocked latches
Static Timing Analysis (STA) team closes timing only on those sequential elements which are clocked. If the enable/clock of the latch comes from the output of a flop, STA team doesn't check it for timing, which may lead to erroneous latching of the data. It will be caught either in simulation or on silicon. This can be prevented if the enable of the latch is a valid clock (gated or ungated).

Figure 5: Un-clocked latch.

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