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Cadence debuts Memory Model for LPDDR5

Posted: 20 Oct 2015     Print Version  Bookmark and Share

Keywords:Cadence Design Systems  LPDDR5  memory model  JEDEC  DRAM 

Cadence Design Systems Inc. has unveiled the Cadence Memory Model for the LPDDR5 standard, which is a verification IP (VIP) product that allows engineers to verify that SoC designs are compliant with the JEDEC interface standard. It also ensures that they can operate correctly in a system with the actual memory components.

Validation of designs using the LPDDR5 memory model reduces the risk of mistakes, rework and delayed production, leading to faster production ramp-up and higher product quality, stated the company.

LPDDR5 is the next generation of low-power DRAM and is geared to speed performance, improve signal integrity and reduce refresh times. It is widely anticipated to be used in both mobile and server applications. Due to its enhanced performance, phones and tablets are expected to gain laptop-class performance, with data centre servers maintaining performance but consuming much less energy.

The Cadence memory model for LPDDR5 is available for pre-order by early adopters, with general availability scheduled for late Q4.

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