DSP cores boost digital signal processing in IoT apps

Synopsys Inc. has introduced the latest members of its ARC EM family of processors. The DesignWare ARC EM9D and EM11D cores implement an enhanced version of the ARCv2DSP instruction set architecture (ISA), combining RISC and DSP processing with support for an XY memory system to boost digital signal processing performance while cutting power consumption.

The cores maximise processing throughput by retrieving instructions and data from memories that are tightly coupled to the processor pipeline, reducing the number of accesses to system memory along with the associated latency and power consumption penalties. The ARC MetaWare Development Toolkit has been enhanced to offer full C/C++ programming support for the cores' DSP instructions and XY memory as well as a rich library of DSP functions to facilitate software development. The cores are optimised for DSP-intensive functions such as sensor fusion, voice detection, speech recognition and audio processing that are common in Internet of Things (IoT) and other embedded applications.

The ARC EM9D and EM11D cores claim to deliver the highest level of digital signal processing performance to date in the ARC EM DSP processor family. All EM DSP cores implement a three-stage pipeline and are ideal for applications with a mixture of control and DSP workloads. The EM9D and EM11D take advantage of regular data access patterns common in signal processing code by integrating separate X and Y memories with hardware support for address generation and DMA to move data in and out of the memories.

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