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Meeting IP requirements of ADAS SoCs

Posted: 18 Sep 2015     Print Version  Bookmark and Share

Keywords:Advanced Driver Assistance Systems  ADAS  SoCs  application processor  LPDDR4 

Advanced Driver Assistance Systems (ADAS) are the fastest growing automotive applications.

Gartner[1] reported this market will increase "from $5.6 billion in 2014 to $10.2 billion in 2018, and that it will achieve a compound annual growth rate (CAGR) of 17.1% between 2013 and 2018.

Accordingly, related semiconductor consumption will increase from $1.38 billion to $2.4 billion during the same period, with a CAGR for 2013 to 2018 of 15.5%."

The increasing demand for safety-critical driver assistance systems for pedestrian detection/avoidance, lane departure warning/correction, traffic sign recognition, surround view, drowsiness monitoring and other applications (figure 1) requires a new class of semiconductor SoCs.

Fuelled by consumer interest and government regulations to improve road safety, auto makers are requiring Tier 1 and semiconductor suppliers to develop SoCs that incorporate the latest multimedia standards, run multiple vision base algorithms, and combine image and radar system sensor data.

To implement the advanced protocols required to meet high performance operation, the ADAS SoCs use leading edge design and process technologies that are more stringent than most high-end consumer applications.

Designers of this new class of ADAS SoCs rely on IP suppliers to help overcome the challenges of implementing the application-specific IP requirements as well as meet the robustness, reliability and safety requirements of automotive applications in shortening design and maturation cycles.

Figure 1: ADAS applications.

ADAS SoC design criteria
The new class of ADAS SoCs has specific design criteria from both the application and systems perspective to ensure an efficient SoC design implementation.

Designers building SoCs for ADAS applications need a combination of high-performance and power-efficient IP functions to help deliver total system throughput and meet the real-time quality-of-service requirements (figure 2).

The application processor performance requires at least 32bit class processors running at over 1GHz. In fact, ADAS SoCs that support multiple vision-based applications are starting to migrate to 64bit processors.

In addition to the high-performance application processor, the SoC requires a separate vision processor to implement latest vision algorithms such as Convolutional Neural Networks (CNN).

An additional graphics processor or customised DSP core handles high-rate pixel processing connected to a multimedia interface such as HDMI or MIPI D-PHY, which together support the increasingly large high-definition displays.

To support the multiple camera and radar sensors supplying image and radar/lidar data, a sensor and control sub-system that offloads the application processor from sensor data management duties will enable the high degree of sensor fusion.

The new generation of ADAS SoCs requires up to 8GB automotive-grade LPDDR4 memory to support the processor application software and extensive system connectivity provided by Ethernet AVB and Time Sensitive Networking (TSN) to support multimedia data traffic.

SoC peripherals such as PCI Express, SATA, UARTs, SPI/QSPI, CAN, and FlexRay offer additional interface connectivity.

Finally, to support cloud connectivity enabled by an external Bluetooth Smart, WiFi or 4G LTE radio IC, the ADAS SoC must include robust hardware-based security protocols for secure boot, secure identification and authentication, encryption, and decryption.

Figure 2: ADAS SoC in 16/14nm process, showing Synopsys DesignWare IP in purple.


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