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Signal chain basics: Grasping noise in ADCs

Posted: 14 Sep 2015     Print Version  Bookmark and Share

Keywords:analogue-to-digital converter  ADC  noise  Noise spectral density  ADS54J60 

As a data converter supplier, we occasionally encounter this question: which is our lowest noise analogue-to-digital converter (ADC)? While the tendency is to assume an ADC with the highest resolution would be the right answer, this is not necessarily the case. But before answering the question, we will discuss different types of noise found in ADCs.

There are many different sources of noise in an ADC, which can be grouped into three different categories based on their frequency characteristics: 1/f noise, white noise, and phase noise. A common way to characterise an ADC is to use an input tone and perform a Fourier transform of the output. Figure 1 shows a simplified frequency spectrum of an ADC output with the different noise characteristics.

Figure 1: Frequency spectrum of an ADC output showing noise characteristics.

Noise spectral density (NSD) is the noise power per unit of frequency, often expressed as dB/Hz. For an ADC, the NSD is usually referenced to the power of a full-scale tone, which is written as dBFS/Hz.

White noise, also known as broadband noise, has a flat PSD. Sources of white noise include quantisation noise, thermal noise, and MOS transistor channel noise. Quantisation noise is due to the error introduced when converting an analogue signal into a digital signal with discrete amplitude values – the noise energy comes from the difference between the analogue and digital values of the signal. Thermal noise is due to thermal movements of electrons in resistors and capacitors. For ADCs with a track and hold capacitor, the thermal noise of the sampling capacitor often dominates the white noise of the ADC. MOS transistor channel noise is due to thermal noise in the MOS transistor channel.

Note that 1/f noise, also known as flicker noise, is due to populating and depopulating of traps in transistors. The PSD of 1/f noise increases inversely with frequency, and therefore is the dominant noise near DC.

Phase noise is due to errors in the sample time of the ADC, and can be due to both the noise on the input clock and the internal ADC clocking circuits. Phase noise modulates with the input signal, and generally has a low frequency component near the input signal and a broadband component that adds to the ADC white noise.

Figure 2 shows the output noise spectrum for a dual-channel, 16bit 1 GSPS ADC (ADS54J60) with a 105MHz input tone (note that the spur level is not accurate in the plot in the interest of highlighting the noise spectrum). Below 5MHz 1/f noise dominates, and within +/–5MHz of the input tone phase noise dominates. The white noise is flat with a value of –159 dBFS/Hz.

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