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Industrial Ethernet comm ASSP integrates Gigabit PHY

Posted: 01 Sep 2015     Print Version  Bookmark and Share

Keywords:Renesas Electronics  ASSP  Gigabit PHY  ARM Cortex-M4  Industry 4.0 

Renesas Electronics Corp. has introduced the R-IN32M4-CL2 industrial Ethernet communication application specific standard product (ASSP) with integrated Gigabit PHY to support the escalating network and factory productivity requirements of Industry 4.0.

The R-IN32M4-CL2 extends the R-IN32M3 platform that incorporates hardware accelerators supporting real-time operating system (RTOS) performance as well as Ethernet packet handling and it improves network performance by up to five times faster than conventional implementations, the company said. The R-IN32M4-CL2 is enhanced with an ARM Cortex-M4 processor with FPU core running at 100MHz, and a single precision floating point unit (FPU) geared for computationally demanding and complex requirements to support process controllers, gateways and IO controllers.


The R-IN32M4-CL2 supports Gigabit Ethernet connectivity with built-in dual Gigabit Ethernet PHYs to reduce the complexity in designing the analogue circuits typically required for gigabit communication. Simplifying the PHY peripheral high-frequency analogue circuit design contributes to reduced development time, risk and lower overall BOM footprint and costs, noted Renesas.

CC-Link IE is a leading industrial Ethernet protocol for high-speed/high-capacity field network that supports Gigabit communication as well as mixed transmission of both equipment control data and management data. This technology will be able to provide the performance required to support the large numbers of sensors and actuators expected with the Industry 4.0 network. The R-IN32M4-CL2 includes the CCLink IE Field slave controller in hardware.

The explosion of sensor nodes will be expected to read many different types of signals, from process data such as temperature, pressure and flow, to digital signals from many IO points. To respond to these needs, the R-IN32M4-CL2 includes an FPU in the CPU core, an 8-channel 10bit ADC, a 16-channel 16bit timer and other functions.

Samples of the R-IN32M4-CL2 will be available in October 2015. Mass production of the R-IN32M4-CL2 is scheduled to begin in March 2016 and is expected to reach a scale of 20,000 units per month in March 2020. (Availability is subject to change without notice.)

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