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GPU enters open-source realm

Posted: 28 Aug 2015     Print Version  Bookmark and Share

Keywords:GPU  GPGPU  open source  processor  MIAOW core 

University of Wisconsin-Madison researchers developed the first general-purpose graphics processor (GPGPU), which is now available as open-source RTL. The device was unveiled at the Hot Chips event in California.

In a separate talk, another academic described an integrated open source processor with a core that's more power-efficient than a similar block from ARM.

Although the GPGPU is in an early and relatively crude stage, it is another piece of an emerging open-source hardware platform, said Karu Sankaralingam, an associate professor of computer science at the University of Wisconsin-Madison. Sankaralingam led the team that designed the Many-core Integrated Accelerator of Wisconsin (MIAOW).

Big companies will someday be built leveraging open source hardware, just as multi-billion-dollar Web giants owe their existence to open source software. "Facebook couldn't have gotten started if it wasn't for PHP," he said, referring to the popular scripting language.

"An open source hardware platform is emerging that has inherent value," said Sankaralingam. "We really need more people contributing to open source hardware to improve the platform layer so there's enough for entrepreneurs to build from it," he said.

One of Sankaralingam's students was working on an out-of-order processor design when AMD released the instruction set architecture of one of its graphics chips. That sparked the idea to build an open-source GPU.

A 12-person team developed the MIAOW core in 36 months. Their goal was simply to create a functional GPGPU without setting any specific area, frequency, power or performance goals.

The resulting GPGPU uses just 95 instructions and 32 compute units in its current design. It only supports single-precision operations. Students are now adding a graphics pipeline to the design, a job expected to take about six months.

An in depth paper on MIAOW is available online but requires special access.


The MIAOW design follow a conventional GPGPU model.

Little MIAOW versus the big cats

Despite its simplicity, MIAOW compares favourably on several benchmarks to AMD's latest high-end chip, Tahiti. However, it also falls far short on other benchmarks.

The design is currently implemented in an FPGA simulation. "A team from Portugal downloaded our materials and got it running—I never even got an email from them—I was shocked," Sankaralingam said.


MIAOW currently implements about 95 instructions and 32 compute units.

"It is surprising we got as far as we did, we punted on the physical design, didn't set hard area or power goals, and using FPGA tools was tedious," he said. Contacts at AMD have "eyeballed [MIAOW] and said none of what we are doing is totally crazy," he added.

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