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Intel CEO: On aiming to become larger than IoT

Posted: 24 Aug 2015     Print Version  Bookmark and Share

Keywords:Intel  IoT  Altera  FPGA  processor 

EE Times: The IoT company.

Krzanich It's different than that. I want to be everything from cars and robots and computers. They are all smart and connected devices. It's much, much bigger than IoT, IoT is too narrow.

Even the XPoint memory we showed is a way to drive more intelligence. As storage gets more like memory there will be all kinds of applications.

On XPoint memory, Moore's Law and EUV

EE Times: Everyone is hungry to know more about what's inside those chips. What is the 3D XPoint material?

Krzanich We started to describe it today. We said it's a high speed switch, a stacked 3D array. People keep asking if its phase change. We've said it uses bulk properties. It's a bit different from phase change. That chemistry is very unique. It's not a pure phase change because it uses bulk material properties.

EE Times: People want you to open up the interface for 3D XPoint DIMMs rather than use a proprietary extension to DDR4. Will you do that?

Krzanich We showed [3D Xpoint] today on a PCI Express standard interface for SSDs. We will continue to push on to standard bus architectures because that is where the volume is.

We do believe there also is an ability to provide a high-speed bus architectures directly to the CPU as well. We haven't defined whether to keep it proprietary or put in in standards bodies. We've been focused on completing the technology, and we're just now starting to ask some of these questions.


Krzanich departed from the practice of done former CEOs by not holding up for the tech paparazzi a wafer from a next-generation process or a next-generation PC CPU.

EE Times: In your job you have to make some tough decisions. How did the so-called tick-tock-tock decision come about for designing three rather than two processor generations for each process node?

Krzanich Most hard decisions come down to pretty simple facts.

What drove this is the longest period of time between lithography shifts in the history of this industry. We are two or three generations late from when we should have gotten EUV. That drives a lot of multi-patterning and complexity of design and creates a lot of defects.

The last two process generations were closer to two-and-a-half than to two years long. So it was simple to look at 10nm and say, we don't have EUV, the number of multi-patterning steps will just go up and the likelihood is it will take two and a half years. It was a hard decision to make.

The reason we didn't label it tick-tock-tock was because we do believe at 7nm there's a high likelihood we can implement EUV and that would shift the whole set of questions about what's driving the two-and-a-half year cadence. I was unwilling to say its two-and-a-half years forever.

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