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SDSoC enables advances in high-level synthesis

Posted: 25 Aug 2015     Print Version  Bookmark and Share

Keywords:Xilinx  SDSoC  SoC  MPSoC  Zynq 

A new tool from Xilinx called SDSoC has been developed to open up SoC and MPSoC capabilities for the first time to embedded system designers in a familiar environment. What this really means is we can develop our embedded application in an eclipse IDE using C, C++ or System C.

To me this is important as the Zynq is a device every embedded system designer should be familiar with and considering for their application. At its heart the Zynq is not a FPGA with embedded processors—like previous generations of FPGA with Power PCs—but a true embedded processor with very flexible interfacing capabilities (DDR, CAN, UART, USB, Giga Bit Ethernet, SPI and I2C to name a few). What separates the Zynq from other embedded processors is the attached programmable logic, and with SDSoC embedded system developers can exploit this pretty simply.

Those familiar with FPGA development may have noticed over the recent years the trend towards high level synthesis (HLS) and have experimented or developed with tools like Vivado HLS. HLS tools allow us to develop algorithms in C, C++ or System C and generate a synthesisable RTL netlist. Obviously this saves significant time in the development life cycle, as it is much faster to generate and verify algorithms in C than HDL.

SDSoC takes the eclipse front end, Vivado HLS, Vivado and a lot of behind the scenes intelligence to create seamlessly the option to accelerate software functions in the attached programmable logic of the device.

Figure 1: Accelerating the function mmult() into the hardware at the click of a button.

So how does it do this? To the user it is really as simple as selecting the function to be accelerated (see above image) and clicking build, of course what happens behind the scenes is much more complex and interesting.

At the heart of the SDSoC tool is the "connectivity framework," which describes the logical and physical connections between the PL (programmable logic) and PS (processor system) sides of the device. The logical and physical connections are provided to SDSoC in the form of a hardware definition and a software definition and is essentially the board support package for the embedded system containing:
 • Clocks – All clocks used within the SDSoC platform must be from the processor clock
 • Resets – The number of resets available
 • Interrupts—The number of interrupts available
 • AXI – The number of AXI and AXI-Streaming connections available
 • Boot Files depending upon the Operating System
 • Library packages
 • Prebuilt hardware definitions – this saves on compile time.

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