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Developing many-core DSP chips, computers for space apps

Posted: 30 Jul 2015     Print Version  Bookmark and Share

Keywords:DSP  satellite  space  communication  processor 

There are nearly 3600 satellites orbiting the earth and are primarily used in weather, navigation, TV broadcast, earth remote sensing and communications applications. Members of the latter category are used to convey communication signals across large distances than cannot be easily linked by a direct line or cable.

Most communication satellites actually act like a mirror: they receive signals from one station on earth, amplify these signals, and send them on to other locations on earth. The point to note here is that, other than amplifying the signal in some cases, most satellites do not perform any actual processing on the received signals.


There are an estimated 3,600 satellites in space, the majority of which perform no processing on the data transferring through them.

Now, imagine a satellite that would not only amplify and reshape the signals it receives, but would also perform some processing on the signals passing through it. For example, de-modulating the signal, performing forward error correction, deciding which direction requires the data and re-modulating it down to earth. Such processing would increase the efficiency of the satellite operation, significantly improve the use of the allocated bandwidth, and add a new level of functionality to these systems.

RC64 many-core architecture

RC64 many-core architecture

With this, and other, challenges in mind, a special European consortium known as MacSpace was established. MacSpace is funded by the European commission under the FP7 Space programme, and it is dedicated to analyse and define the applications and benchmarks to be used in space. This includes designing a unique processor, which will be able to run those applications efficiently and will be protected against the effects of radiation. The programme is expected to take just less than three years (until August 2016).

Processing huge amounts of data with the RC64 architecture

In order to process huge amounts of data, a novel rad-hard 64-core signal processing chip (many core design) is being developed by the MacSpace consortium. This device targets DSP performance of 75 GMACs (16bit), 150 GOPS, and 40 single-precision GFLOPS, all while dissipating less than 10W.

The many-core architecture is depicted below. A central scheduler assigns tasks to a number of DSPs, each of which executes its task from its cache storage, accessing shared memory only when needed. When task execution is completed, the DSP notifies the scheduler, which can subsequently assign a new task to that processor. Access to off-chip streaming channels, DDR2/3 memory and other interfaces happens only via programmable DMA channels.

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