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RISC-V reveals advantages over x86, ARM

Posted: 15 Jul 2015     Print Version  Bookmark and Share

Keywords:x86  ARM  RISC-V  open source  Z-scale 

The University of California, Berkeley recently hosted a workshop highlighting improvements with RISC-V, an open source core that seems to uncover architectural advantages over commercial x86 and ARM cores.

In late June, Berkeley held a workshop to get to know what research has been underway on RISC-V. RISC-V is an open instruction set architecture (ISA) originally developed at Berkeley and based on established reduced instruction set computing principles. It is a minimal, modular ISA ready for hardware implementation, freely available to both academia and industry.

The workshop was sold out with 120 attendees representing 30 companies and 20 universities. The Berkeley speakers were in the minority, with other speakers from Australia, England, India, Italy and Switzerland.

It appears RISC-V is experiencing a bandwagon effect. Conversations in the hallways suggested multiple commercial efforts may be underway. The speculation was primarily due to the very active participation from the commercial engineering community.

The workshop's programme emphasised past work and achievements but put even more emphasis on future challenges and research directions to pursue. Motivating talks covering multiple areas are fundamental to any successful systems workshop and particularly one of this type.

Three of the first-day's presentations gave proposals on compressed and vector extensions as well as on a class of architecture that my colleagues termed privileged. Krste Asanovic, Dave Patterson and Berkeley colleagues outlined a number of goals and rationales behind RISC-V compressed (RVC), as well as proposed a number of new extended RVC instructions.

It is an open question whether the current draft set of those instructions will be sufficient to cover all possible future scenarios or if more RVC instructions will be needed as systems evolve. In addition, further work likely will be needed to figure out not only the relative values of the instructions but also whether those values change as systems evolve whether at the level of 32bit or 64bit addressing. Nevertheless, the initial data shows RISC-V has the smaller code size than x86 and ARM.

In regard to a privileged architectural class, virtualisation (in time, memory and etc.) permeates all levels of the ISA. The architecture offers a set of modular and clearly delineated levels of software for applications, hypervisors and the operating systems. The architecture lends itself to simplicity at the embedded systems level, to size/scale at the virtual/memory management level, and to low implementation cost.

Also on the first day, colleagues at the University of Cambridge presented their lowRISC architecture on the first day of the event. One of their goals is to bring the benefits of open source software to silicon by producing a complete open-source reference system-on-chip design for others can build on.

Presenters described other specific chip design efforts on the second day of the workshop. Z-scale is a tiny RISC-V 32bit core generator for microcontrollers and embedded systems, similar to ARM Cortex M0/M0+/M4, integrating AHB-Lite interconnects. Z-scale shows advantages over ARM Cortex-M0 architecture in performance, area efficiency, frequency, voltage and dynamic power.

Open source implementations of Z-scale at Berkeley are available in Verilog and Chisel, which is a hardware-device-language embedded in Scala. Going forward, the core generator will be integrated as a component of the Rocket chip generator.

The Berkeley Out-of-Order Machine (BOOM) is a work-in-progress. Essentially, it is a RISC-V RV64G-based out-of-order superscalar application core with higher performance, much better area efficiency, and comparable frequency-wise to the ARM Cortex-A9.

Raven3 is a 28nm RISC-V vector processor with on-chip DC/DC convertors. Maximising energy efficiency is the main goal of this architectural paradigm.

- Saleh Elmohamed
  University of California, Berkeley





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