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IBM reveals III-V FinFETs on silicon substrate

Posted: 23 Jun 2015     Print Version  Bookmark and Share

Keywords:IBM  silicon  Imec  FinFET  FinFETs 

The previous IBM researchers using SOI wafers had multi-gate metal-oxide-semiconductor (MOS) field-effect transistors (FETs), but they were not regular FinFETs, because there were too many defects from the lattice mismatch. However, the CELO process has very few InGaAs defects, allowing IBM to build both planar and finned FETs using a III-V material as their high-speed channel above buried oxide (BOX).

"Other approaches use aspect ratio trapping, such as Imec, instead of growing on the wafer, but our CELO process goes one step further by just beginning growth in a trench, where there are many defects, then turning the growth 90 degrees when it comes out of the trench where the planar growth produces very few defects," Fompeyrine said.

CELO approach

The table demonstrates IBM's belief that it has finally solved all the outstanding problems (green) in depositing III-V transistor channels. (Source: IBM)

The CELO approach resulted in gate-first self-aligned FinFETs with excellent electrical characteristics that outperformed similar sized silicon transistors. The InGaAs FinFETs had 100nm long gates, 50nm wide fins, 250nm wide contacts and was 30nm thick. Since no processes other than standard CMOS were used, IBM claims the III-V on silicon CELO technology has "significant potential" for high-volume manufacturing at advanced CMOS nodes.

- R. Colin Johnson
  EE Times

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