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IBM reveals III-V FinFETs on silicon substrate

Posted: 23 Jun 2015     Print Version  Bookmark and Share

Keywords:IBM  silicon  Imec  FinFET  FinFETs 

The entire semiconductor industry is trying to find a way to exploit the higher electron mobility of indium, gallium and arsenide (InGaAs) without switching from silicon substrates, including the leaders at Intel and Samsung. IBM has demonstrated how to achieve this with standard CMOS processing.

Last month IBM showed a technique of putting III-V compounds of InGaAs onto silicon-on-oxide (SOI) wafers, but now a different research group claims to have found an even better way that uses regular bulk-silicon wafers and have fabricated the InGaAs-on-silicon FinFETs to prove it.

"Starting from a bulk silicon wafer, instead of SOI, we first put down an oxide layer and make a trench through to the silicon below, then grow the indium gallium arsenide from that seed; it's a very manufacturable process," said Jean Fompeyrine, manager of advanced functional materials, IBM. Fompeyrine did the work with Lukas Czornomaz, an advanced CMOS scientist with IBM Research.

CMOS manufacturing

The InGaAs grows upward from a seed with many defects (left) then continues horizontally across the wafer virtually defect free, after which the ends are etched off leaving a perfectly non-strained crystalline transistor channel (green) of III-V material atop a buried oxide (BOX) on a standard silicon substrate (no need for silicon on insulator, SOI) with a metal source, drain and gate (grey) using a high-k dielectric (red) all surrounded by an interlayer dielectric (yellow) of silicon dioxide. (Source: IBM)

Using a method similar to that of Belgium-based microelectronics research centre Imec, IBM's process has a twist that makes all the difference. Imec's growth was vertical only, but IBM only begins vertically then coaxes the InGaAs to turn horizontal and inward. The process stops making the lattice mismatch defects it was making during the vertical column growth pattern, according to Fompeyrine.

"Our method uses confined epitaxial overgrowth, or CELO, which results in InGaAs epitaxial structures with very low defectivity, which fulfills the requirements of both ultra-thin-body and fin-based advanced CMOS nodes," Fompeyrine said.

CELO

Here IBM demonstrates that its confined epitaxial lateral overgrowth (CELO) technique even works with FinFETs on a standard silicon substrate. (Source: IBM)


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