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Understanding parasitic extraction of FinFETs

Posted: 15 Jun 2015     Print Version  Bookmark and Share

Keywords:FinFETs  Memory  parasitics  Parasitic resistance  CPU 

Table 1 compares the extraction runtime required for a 16 nm memory design using the boundary condition technique and traditional extraction of the full 4x8 array, and a 1M instance. In each case, we used the Calibre xACT 3D field solver extraction tool, which provides high accuracy but employs efficient parallelisation techniques to optimise multi-CPU runtime performance.

Running a single cell with boundary conditions versus a flat 4x8 run provides a runtime improvement of 9.2X. For much larger memory blocks, there is a proportionally greater advantage to using this methodology. The runtime of a rule-based extraction tool is expected to be similar to a single cell run with boundary conditions, although much less accurate. Flat extraction of all 1M instances (6.5 million devices) provides the highest accuracy with a runtime of 6.1 hrs using 16 CPUs, which reflects a highly scalable field solver performance supporting overnight turnaround.

Table 1: Comparing the boundary condition extraction technique to flat extraction for large memory structures using the Calibre xACT 3D tool.

There is some accuracy degradation when using the boundary condition method vs. extracting the whole block flat. Capacitance of the single cell was compared with the full 4x8 array with the capacitance divided by either 4 or 8 depending on whether the line was going in a horizontal or vertical direction). The accuracy degradation due to the isolation of a single cell is shown in Table 2 below.

Table 2: Accuracy boundary condition technique compared to full flat extraction using the Calibre xACT 3D tool.

Running flat parasitic extraction with a field solver is always the most accurate solution, but other good alternatives include running a cell or subset array using boundary conditions, or running with a rule-based extraction tool. A rule-based extraction tool can be used during the iterative design cycle, when quick turn-around times are required, and a field solver can be used for bit cell design and final sign-off, ensuring the highest accuracy possible.

Using a field solver for extraction during all phases of a memory design, from bit cell design, to block characterisation, to full chip sign-off ensures that the chip will work to specification when it is manufactured. The boundary condition extraction technique can reduce field solver runtime by orders of magnitude with only minor accuracy degradation on the order of 1-4 per cent compared to full flat extraction.

[1] Yoon, Jun-Sik, et al. "Extraction of source/drain resistivity parameters optimised for double-gate FinFETs." Japanese Journal of Applied Physics 54.4S (2015): 04DC06.

About the author
Karen Chow is a technical marketing engineer in the Design-to-Silicon division of Mentor Graphics Corp. in Wilsonville, Oregon, focusing on driving parasitic extraction development in analogue and RF design flows. Prior to joining Mentor Graphics, Karen worked in the telecommunications and EDA industries, designing analogue ICs and supporting EDA tool development. She received her Bachelor of Science degree in electrical engineering from the University of Calgary, and her MBA from Marylhurst University.

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