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Cadence synthesis engine delivers 5x faster turnaround time

Posted: 09 Jun 2015     Print Version  Bookmark and Share

Keywords:Register-transfer level  RTL  physical synthesis  Genus Synthesis 

Cadence Design Systems developed the Genus Synthesis Solution, a next-generation register-transfer level (RTL) synthesis and physical synthesis engine, incorporating a multi-level massively parallel architecture. It may deliver up to five times faster synthesis turnaround time and scale linearly beyond 10M.

In addition, the tool's new physically aware context-generation capability is said to reduce iterations between unit- and chip-level synthesis by two times or more, factoring up to a to 10 times improvement in RTL design productivity.

The new tool is architected around three levels of parallelism together with adaptive scheduling so as to support the timing-driven distributed synthesis of complex designs across not only multiple cores but also across multiple machines, all transparently to the user.


What's more, the complete timing and physical context for any subset of a design can be extracted and used to drive RTL unit-level synthesis with full consideration of chip-level timing and placement, significantly reducing iterations between chip-level and unit-level synthesis runs.

The Genus Synthesis Solution shares a unified global routing with Cadence's Innovus Implementation System, enabling a tight correlation of both timing and wirelength to within 5 per cent from synthesis to place and route.

For design optimisation, it incorporates a new datapath optimisation engine that concurrently considers many different datapath architectures across the whole design and then leverages an analytical solver to pick the architectures that achieve the globally optimal performance, power and area (PPA). This engine delivers up to 20 per cent reduction in datapath area without any impact on performance, claims Cadence.

- Julien Happich
  EE Times Europe

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