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EE Times-India > EDA/IP

Low-power PCIe 3.1 IP sol'n targets mobile SoCs

Posted: 25 May 2015     Print Version  Bookmark and Share

Keywords:Synopsys  mobile SoC  PCI Express  PCIe 3.1  PHY IP 

Synopsys Inc. has unleashed what it flaunts as the industry's lowest power controller and PHY IP solution for PCI Express (PCIe) 3.1 specification that remarkable cuts both active and standby power consumption for mobile SoCs. According to the company, the silicon-proven Synopsys DesignWare IP for PCIe 3.1 specification combines L1 sub-states along with power gating techniques including the use of power switches, power islands or retention cells to reduce standby power to less than 10μW/lane.

In addition, supply under drive, a novel transmitter design and equalisation bypass schemes cut active power to well below 5mW/Gb/lane while meeting the PCIe 3.1 electrical specification. By providing a controller and PHY IP solution for PCIe technology that is optimised to deliver the lowest power consumption, Synopsys enables designers to incorporate the necessary functionality into their SoCs and extend the battery life of mobile devices, noted the company.

The DesignWare PHY IP for PCIe 3.1 technology exceeds required PCIe channel performance with multi-phase-locked loops (MPLLs), Feed Forward Equalisation (FFE), Continuous Time Linear Equalisation (CTLE) and programmable Decision Feedback Equalisation (DFE) to enhance signal integrity across high loss and bumpy channels, detailed Synopsys. Separate Refclk Independent SSC (SRIS), reference clock forwarding and PCI Express architecture aggregation and bifurcation provide flexibility and scalability for high-speed SoCs. The PHY's automatic test equipment (ATE) test capabilities, small area and optional wirebond packaging reduce overall bill of materials (BOM) cost, added the company.

As part of the complete solution, the DesignWare Controller IP for PCI Express 3.1 specification supports L1 sub-states in conjunction with power islands or retention cells for up to 95 per cent lower leakage power during standby mode and very low exit latency, enabling faster wake up time. To reduce active power, the controller supports system-level power management features including latency tolerance reporting (LTR), optimised buffer flush/fill (OBFF) and dynamic power allocation (DPA). In addition, Synopsys Verification IP (VIP) for the PCIe architecture combined with SystemVerilog source code test suites support the validation of low-power scenarios. The VIP provides controls to enter, switch between and exit low-power sub-states. It monitors low-power states, and the test suites provide a dedicated set of tests to validate L1 sub-states functionality.

The low-power DesignWare Controller and PHY IP for PCIe 3.1 technology are available. The Verification IP for PCIe 3.1 architecture as well as DesignWare IP Prototyping Kits for PCIe 3.1 Root Complex and for PCIe 3.1 Endpoint are also available.

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