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Significance of piling to packaging manufacturing

Posted: 15 May 2015     Print Version  Bookmark and Share

Keywords:flip chip ball grid array  FCBGA  SerDes  thermal interface material  plated-through holes 

The adage "bigger, faster, stronger" is not only pushing athletes in professional sports. These same attributes are driving electronic flip chip ball grid array (FCBGA) packages (figure 1) to domains never before realised.

Form factors are becoming bigger to increase I/O connections for meeting signal and power integrity needs, faster to meet SerDes (Serialiser / Deserialiser) demands, and stronger to withstand reliability requirements across both automotive and commercial applications. This makes package supplier choice, assembly bill of materials (BoM) and assembly process flow quintessential prerequisites to assure first-time qualification success across various FCBGA packaging technologies.

To accomplish these performance enhancements, intriguing combinations are being constructed at the chip to package level. For example, with 28-nm silicon node designs, C4 bump pitch can be as small as 150µm. To effectively route traces throughout the organic chip carrier (or substrate), line widths can hover at 13/14 (lines/space) depending on substrate manufacturing tolerances.

Figure 1: Representative FCBGA package.

And depending on cost demands and end customer applications, routing density can impact die dimensions (in terms of x and y size, aspect ratio and thickness), core thicknesses, second level interconnect pitch, heat spreader dimensions, and assembly bill of materials (BoMs), to name a few. If these interactions are not recognised, packaging engineers are called in to develop (depending on form factor) novel solutions to combat an increased routing density aftermath.

In addition, failure to grasp a fundamental understanding of these interactions can affect high-volume manufacturing (HVM) assembly yield and package reliability. Examples of HVM yield loss can include warpage-driven effects such as:
 • CTE mismatch between dissimilar materials within the package structure, where deltas in co-planarity of ball grid array (BGA) balls can affect test and surface mount (SMT) yields. See figure 2 showing warpage requirements at peak processing temperature.
 • Bump shorting caused by concavity or convexity of the package

Figure 2: Package warpage at peak processing temperature (per ITRS 2012).

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