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DFT boot camp, Part 2: Test compression

Posted: 14 May 2015     Print Version  Bookmark and Share

Keywords:design-for-test  DFT  test software  automatic test-pattern generation  ATPG 

The size of designs continues to increase and IC manufacturers are pushing for higher test quality, especially in mission-critical applications such as transportation and medicine. More advanced nodes also require new types of tests to catch more subtle defects. The result: exploding test pattern set sizes that result in longer test times and the need for more tester capacity for a given device ship rate. That drives up manufacturing cost.

To help manage the size of test patterns without sacrificing test quality, design for test (DFT) software tools employ compression techniques to reduce the size of the patterns that have to be transferred to the device under test (DUT). The technique involves adding a small amount of circuitry to the DUT and special processing of the test patterns when they are generated by the automatic test pattern generation (ATPG) software. Test compression levels of two orders of magnitude compared to uncompressed patterns are routinely achieved. Once compressed test patterns are expanded within the device under test, they can be applied to a much higher number of shorter internal scan chains than is possible for patterns applied externally. Thus, compression also results in reduced test times.

Figure 1 shows a basic block-level implementation of the on-chip compression scheme and how it connects to the tester. The core design and its scan chains (see part 1 of this series) are in the middle of the upper block. The additional on-chip logic includes a decompressor on the input side, which expands the compressed patterns and loads them into the scan chains within the DUT. A compactor on the output side captures and compresses the test results and returns the data to the tester for comparison against expected results. This logic is only active in the scan path during test and doesn't affect the IC's functional design or performance.

Figure 1: Example of on-chip test compression logic.

Unknown states
For most scan test pattern results, some number of Xs, or unknown values, are captured in the scan cells. These Xs come from many sources such as uninitialized flip-flops and memories. If not handled properly, these Xs cause big problems because they can mask the captured response values that need to be observed for each test pattern. This problem leads to a decrease in test coverage and test compression levels. In the general case, designers need to modify the design to eliminate the sources of Xs. Advanced test compression solutions, however, have methods to block these Xs by using scan-chain masking techniques. So high test coverage and compression levels can still be obtained.

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